Donald A Priore, Age 6411 Canterbury Ln, Groton, MA 01450

6408401, Jun 18, 2002

Nov 13, 1998

09/191679

Dilip K. Bhavsar - Shrewsbury MA
Donald A. Priore - Maynard MA

Compaq Information Technologies Group, L.P. - Houston TX

H02H 305

714 7, 714 6, 714 8, 714710, 714711, 714723

A self-repair method for a random access memory (RAM) array comprises writing a value to the memory array, reading a value from the memory array and comparing the read and write values to identify faulty memory cells in the memory array. An address of a newly-discovered faulty memory cell is compared to at least one address of at least one previously-discovered faulty memory cell. The address of the newly discovered faulty memory cell is stored if a column or row address of the newly-discovered faulty cell does not match any column or row address, respectively, of a previously-discovered faulty memory cell. Flags are set to indicate that a spare row or a spare column must replace the row or column, respectively, identified by the address of the previously-discovered faulty memory cell, if the row or column address of the newly-discovered memory cell matches the respective row or column address of the previously-discovered faulty memory cell. Spare rows and columns that have been indicated by the flags as requiring replacement are allocated to replace faulty rows and columns respectively. The remaining spare rows and columns whose row and column addresses respectively have been stored are then allocated.

6807186, Oct 19, 2004

Jan 17, 2002

10/052233

William J. Dally - Stanford CA
John Edmondson - Arlington MA
Donald A. Priore - Groton MA
Ephrem Wu - San Mateo CA
John W. Poulton - Chapel Hill NC

LSI Logic Corporation - Milpitas CA

H04L 1228

370413, 370360

A single-stage grooming switch is provided for switching streams of multiplexed traffic, such as SONET STS-48, in both time and space domains. In particular, the switch implements a distributed demultiplexing architecture for switching between any input timeslot to any output timeslot at a reduced layout size. Furthermore, the distributed demultiplexing architecture results in low latencies being associated with reconfiguration of output permutations on the order of nanoseconds.

7100020, Aug 29, 2006

May 7, 1999

09/674864

Thomas B. Brightman - North Hampton NH, US
Andrew T. Brown - Fort Collins CO, US
John F. Brown - Wellesley MA, US
James A. Farrell - Harvard MA, US
Andrew D. Funk - Boxford MA, US
David J. Husak - Windham NH, US
Edward J. McLellan - Holliston MA, US
Mark A. Sankey - Acton MA, US
Paul Schmitt - Princeton MA, US
Donald A. Priore - Maynard MA, US

Freescale Semiconductor, Inc. - Austin TX

G06F 15/00

712 18, 712 13, 712 14, 712 15, 712 16, 712 17, 712 35, 712 36, 712 37, 709231, 709232, 709236, 709238

An integrated circuit () for use in processing streams of data generally and streams of packets in particular. The integrated circuit () includes a number of packet processors (), a table look up engine (), a queue management engine () and a buffer management engine (). The packet processors () include a receive processor (), a transmit processor () and a risc core processor (), all of which are programmable. The receive processor () and the core processor () cooperate to receive and route packets being received and the core processor () and the transmit processor () cooperate to transmit packets. Routing is done by using information from the table look up engine () to determine a queue () in the queue management engine () which is to receive a descriptor () describing the received packet's payload.

7647472, Jan 12, 2010

Aug 25, 2006

11/510545

Thomas B. Brightman - North Hampton NH, US
Andrew D. Funk - Boxford MA, US
David J. Husak - Windham NH, US
Edward J. McLellan - Holliston MA, US
Andrew T. Brown - Fort Collins CO, US
John F. Brown - Wellesley MA, US
James A. Farrell - Harvard MA, US
Donald A. Priore - Maynard MA, US
Mark A. Sankey - Acton MA, US
Paul Schmitt - Princeton MA, US

Freescale Semiconductor, Inc. - Austin TX

G06F 15/76

712 10, 370389, 370412, 37039572

An integrated circuit () for use in processing streams of data generally and streams of packets in particular. The integrated circuit () includes a number of packet processors (), a table look up engine (), a queue management engine () and a buffer management engine (). The packet processors () include a receive processor (), a transmit processor () and a risc core processor (), all of which are programmable. The receive processor () and the core processor () cooperate to receive and route packets being received and the core processor () and the transmit processor () cooperate to transmit packets. Routing is done by using information from the table look up engine () to determine a queue () in the queue management engine () which is to receive a descriptor () describing the received packet's payload.

7933760, Apr 26, 2011

Mar 25, 2008

12/054471

Russell Schreiber - Austin TX, US
Keith Kasprak - Austin TX, US
Donald A. Priore - Groton MA, US

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 17/50

703 14, 703 2, 702 57, 702179

A method of simulating operation of a bitcell includes determining sensitivities of a bitcell model to different component characteristics and device parameters, such as device temperature, operating voltage, and process characteristics. The determined sensitivities are normalized, so that each normalized value represents the relative sensitivity of the bitcell, under the simulated device parameters, to the component characteristic associated with the value. The normalized sensitivity values can be scaled based on a tolerance factor, and the adjusted sensitivities used to model the behavior of each component of the bitcell in subsequent simulations.

8589661, Nov 19, 2013

Dec 7, 2010

12/962113

Mike Butler - San Jose CA, US
Donald A. Priore - Groton MA, US
Steven Beigelmacher - Somerville MA, US

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 9/30

712210

A method and apparatus are presented for processing a stream of information, including preprocessing the stream, which includes partitioning the stream into packets of interest; determining boundaries for the packets of interest, wherein a packet boundary is either a start location or an end location for a packet; and making a record of the packet boundaries by setting a hint bit in a hint bit vector, a location of the hint bit within the hint bit vector corresponding to a position of the packet in the stream. The hint bit vector is split into two or more vectors, where the hint bits are assigned to one of the vectors on an alternating basis. The packets of interest are processed corresponding to the hint bits assigned to each vector in parallel over multiple clock cycles, wherein an original order of the packets of interest is maintained in the stream.

2012016, Jun 28, 2012

Dec 22, 2010

12/976034

Edward J. McLellan - Holliston MA, US
Magiting M. Talisayon - Newton MA, US
Donald A. Priore - Groton MA, US

ADVANCED MICRO DEVICES, INC. - Sunnyvale CA

G06F 9/30

712245, 712E09016

Techniques for switching or parking threads in a processor including a plurality of processor cores that share a microcode engine are disclosed. In a dual-core or multi-core system, a front end, (e.g., microcode engine), of the processor cores may be shared by the two or more active threads in order to reduce the area, cost, or the like. A currently running thread may be put to a sleep state and execution of another thread may be initiated when a yield microcode command issues while the currently thread is running. The thread may be resumed on a condition that the second thread goes to a sleep state, yields, exits the processing, etc. Alternatively, a thread may be put to a sleep state when a sleep microcode command issues which is programmed to occur when the thread needs to wait for an event to occur.

2012016, Jun 28, 2012

Dec 22, 2010

12/975585

Kevin M. Gillespie - Pembroke MA, US
Timothy J. Correia - Burlington MA, US
Donald A. Priore - Groton MA, US

ADVANCED MICRO DEVICES, INC. - Sunnyvale CA

G06F 9/455

716107

A method is disclosed of determining a likelihood of failure of a circuit made in accordance with a circuit design based on at least one variable derived from measurements of a fabricated component or component combination included in the circuit design. Also disclosed is a processor configured to perform the method and a computer-readable medium storing method instructions.