Abbas I Attarwala, Age 58Union City, CA

Abbas Attarwala Phones & Addresses

Union City, CA

133 Ray Ct, Fremont, CA 94536 (510) 797-9389 (510) 790-7994

27379 Marigold Ct, Hayward, CA 94545

Dallas, TX

Mountain View, CA

Tracy, CA

Alameda, CA

133 Ray Ct, Fremont, CA 94536

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Work

Position: Administrative Support Occupations, Including Clerical Occupations

Education

Degree: Bachelor's degree or higher

Emails

Mentions for Abbas I Attarwala

Publications & IP owners

Us Patents

Electronic Package And Method

US Patent:
7105931, Sep 12, 2006
Filed:
Jan 6, 2004
Appl. No.:
10/753115
Inventors:
Abbas Ismail Attarwala - Fremont CA, US
International Classification:
H01L 23/48
US Classification:
257783, 257778
Abstract:
An electronic package substrate for an electronic package that includes an adhesive bonding member having two planar surfaces and an orifice there through for receiving a chip and a circuitized member having two planar surfaces, one surface being bonded to one of the planar surfaces of the bonding member, the circuitized member being electrically connectable to the chip. The electronic package substrate is fabricated for an electronic package for either a wire bonded chip, a tab bonded chip, or a flip chip.

Method For Making Electronic Packages

US Patent:
7575955, Aug 18, 2009
Filed:
Nov 21, 2005
Appl. No.:
11/284552
Inventors:
Abbas Ismail Attarwala - Fremont CA, US
Assignee:
Ismat Corporation - Union City CA
International Classification:
H01L 21/00
US Classification:
438118, 438107, 438108, 438456, 257E21499, 257E21514
Abstract:
A process for fabricating an electronic package for a Thermally Enhanced BGA package including the steps of fabricating a thermally conductive support member, an adhesive bonding member, and a circuitized member; sandwiching the members together, forming a cavity therein; bonding adhesively the members together with heat and pressure; bonding adhesively a chip to the support member within the cavity; and connecting electrically the chip to the circuitized member. A process for fabricating an electronic flip chip package, including the steps of fabricating an adhesive bonding member, a flip chip, and a circuitized member; aligning the members with respect to each other; sandwiching the members together; bonding the members together with heat and pressure; and connecting electrically the flip chip to the circuitized member.

Low Stress Ball Grid Array Package

US Patent:
5586010, Dec 17, 1996
Filed:
Mar 13, 1995
Appl. No.:
8/403164
Inventors:
Masood Murtuza - Sugarland TX
Abbas I. Attarwala - Mountain View CA
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H05K 111
H05K 114
H01R 909
US Classification:
361751
Abstract:
The ball grid array package (10) uses a flexible base (30) having a substantially flat center plate (34) disposed at a first level coupled to a substantially flat base plate (32) disposed at a second level. The center plate (34) is coupled to the base plate (32) by a plurality of flexible narrow straps (36-38) arranged substantially surrounding the center plate (34). The flexible base (30) accommodates the thermal expansion in the pedestal (18) caused by the powered up integrated circuit (16) so that the rest of the package does not expand and induce stress in the solder joint between the ball grid array (12) and the printed circuit board (14).

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