Abhijeet C Kulkarni, Age 471835 E Crescent Way, Chandler, AZ 85249

Abhijeet Kulkarni Phones & Addresses

1835 E Crescent Way, Chandler, AZ 85249

Tempe, AZ

Mentions for Abhijeet C Kulkarni

Abhijeet Kulkarni resumes & CV records

Resumes

Abhijeet Kulkarni Photo 29

R And D Director

Location:
Chandler, AZ
Industry:
Semiconductors
Work:
Nxp Semiconductors May 2015 - Jan 2018
R and D Manager
Nxp Semiconductors May 2015 - Jan 2018
R and D Director
Nxp Semiconductors Jan 2014 - May 2015
Principal Design Engineer
Nxp Semiconductors Aug 2007 - Jan 2014
Senior Digital Design Engineer
Nxp Semiconductors Austria Mar 2001 - Aug 2007
Digital Design Engineer
Nxp Semiconductors Feb 2001 - Jul 2001
Junior Digital Design Engineer
Education:
Indian Institute of Technology, Bombay 1999 - 2001
Masters, Master of Technology, Design
Department of Technology, Savitribai Phule Pune University 1994 - 1998
Bachelor of Engineering, Bachelors
Skills:
Integrated Circuit Design, Ic, Asic, Digital Signal Processors, Semiconductors, Soc, Mixed Signal, Digital Ic Design, Arm, Cmos, Rtl Coding, Test Engineering, Analog, Usb, Application Specific Integrated Circuits, System on A Chip, Integrated Circuits, Dft, Functional Verification, Verilog, Embedded Systems, Debugging, Vhdl, Rtl Design
Languages:
Marathi
Hindi
English
Dutch
Abhijeet Kulkarni Photo 30

Abhijeet Kulkarni

Abhijeet Kulkarni Photo 31

Abhijeet Kulkarni

Abhijeet Kulkarni Photo 32

Abhijeet Kulkarni

Location:
United States
Abhijeet Kulkarni Photo 33

Abhijeet Kulkarni

Location:
United States
Abhijeet Kulkarni Photo 34

Abhijeet Kulkarni

Location:
Phoenix, Arizona Area
Industry:
Semiconductors
Abhijeet Kulkarni Photo 35

Abhijeet Kulkarni - Glendale, AZ

Work:
Aggreko LLC Jun 2014 to 2000
Pricing and CRM project developer intern
Henkel North America - Phoenix, AZ Jan 2014 to Mar 2014
Consumer Insights and Pricing Student Consultant
Louis Vuitton - DFS - Phoenix, AZ Jan 2014 to Mar 2014
Marketing Strategy and Marketing Communication Student Consultant
Aggreko LLC - Pune, Maharashtra Jul 2011 to Jun 2013
Marketing Executive - India
Education:
MGM Institute of Management - Aurangabad, Maharashtra Jun 2011
MBA in Marketing
PES College of Engineering - Aurangabad, Maharashtra Jun 2009
BS in Electrical, Electronics & Power Engineering
Thunderbird School of Global Management - Phoenix, AZ
Master in Global Marketing
Skills:
Strategic Marketing, Product Marketing, Brand Management, Project Management, Market Analysis, Marketing Communication
Abhijeet Kulkarni Photo 36

Abhijeet Kulkarni - Glendale, AZ

Work:
Aggreko Energy Rental India Private Ltd Jul 2011 to Jun 2013
Marketing Executive - India
Education:
MGM Institute of Management - Aurangabad, Maharashtra Jun 2011
MBA in Marketing
PES College of Engineering - Aurangabad, Maharashtra Jun 2009
BS in Electrical, Electronics & Power Engineering
Thunderbird School of Global Management - Phoenix, AZ
Master in Global Marketing

Publications & IP owners

Us Patents

Serial Bus Apparatus With Controller Circuit And Related Uses

US Patent:
2017019, Jul 6, 2017
Filed:
Jan 6, 2016
Appl. No.:
14/989378
Inventors:
- Eindhoven, NL
Madan Mohan Reddy Vemula - Tempe AZ, US
Abhijeet Chandrakant Kulkarni - Chandler AZ, US
Kenneth Jaramillo - Gilbert AZ, US
International Classification:
G05F 3/02
H02J 4/00
Abstract:
Low power solutions can be provided in a serial bus system with a logic controller circuit. The logic controller circuit can include analog circuitry that includes a plurality of analog components and trimming circuitry for configuring the analog components. Digital circuitry can be configured to switch between an active mode and a hibernation mode, wherein the hibernation mode consumes less current than the active mode. A voltage regulator circuit can be configured to generate a regulated voltage from a supply voltage. A reset generation circuit can be configured to determine that the supply voltage has reached a first threshold voltage level and enable the voltage regulator circuit. When the regulated voltage has reached a second threshold voltage level and the supply voltage has reached a third threshold voltage level, the digital circuitry can be switched to the active mode.

Communications For Power Delivery Solutions

US Patent:
2017011, Apr 27, 2017
Filed:
Oct 23, 2015
Appl. No.:
14/921276
Inventors:
- Eindhoven, NL
Madan Mohan Reddy Vemula - Tempe AZ, US
Sharad Murari - Gilbert AZ, US
Abhijeet Chandrakant Kulkarni - Chandler AZ, US
Krishnan Tiruchi Natarajan - Cuptertino CA, US
International Classification:
G06F 1/26
G06F 13/10
Abstract:
A protocol can specifie a power-sourcing voltage range that indicates power sourcing capabilities. Additional power sourcing capabilities can be communicated using voltage variations within the power-sourcing voltage range. A power-sourcing device can provide power to an external power-sinking device over a wired connection containing a plurality of wires. A voltage control circuit can be configured to drive a voltage over a wire of the plurality of wires. Processing circuitry can communicate, using the voltage control circuit, first power-sourcing capabilities to the external power-sinking device by setting the voltage over the wire to a value within the power-sourcing voltage range. The processing circuitry can also communicate, using the voltage control circuit, the additional power sourcing capabilities of the power-sourcing device using voltage variations on the wire, the voltage variations maintaining voltage on the wire within the power-sourcing voltage range.

Bus Interfaces With Unpowered Termination

US Patent:
2017009, Mar 30, 2017
Filed:
Sep 28, 2015
Appl. No.:
14/868044
Inventors:
- Eindhoven, NL
Ahmad Yazdi - Chandler AZ, US
Abhijeet Chandrakant Kulkarni - Chandler AZ, US
International Classification:
H02J 1/00
H02M 7/04
Abstract:
A system including a device that is configured to communicate current sourcing capabilities to an external power source over a wired connection containing a plurality of wires. The device includes a power supply circuit configured to provide operating power for the device. A first pull-down circuit is configured to provide a pull-down for a particular wire of the wired connection using a first resistive element that is actively trimmed using the operating power. A second pull-down circuit includes at least one transistor that, in the absence of the operating power, is configured to enable a current path, in response to a gate voltage generated from a voltage on the particular wire, between the particular wire and a second resistive element.

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