Ahmad Houssam Tarakji, Age 574851 Kokomo Dr UNIT 5524, Sacramento, CA 95835

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Ahmad Tarakji Phones & Addresses

4851 Kokomo Dr APT 5524, Sacramento, CA 95835

San Diego, CA

Columbia, SC

6093 Zabaco Ter, Beaverton, OR 97007

San Francisco, CA

Hayward, CA

Moscow, ID

3535 Lebon Dr APT 5103, San Diego, CA 92122

Education

Degree: High school graduate or higher

Mentions for Ahmad Houssam Tarakji

Ahmad Tarakji resumes & CV records

Resumes

Acting Chief Executive Officer

Location:

San Diego, CA

Industry:

Semiconductors

Work:

Private Consulting Feb 1, 2012 - Feb 2012
Senior Device and Process Integrator Engineer Acting Ceo For Solidi Technologies Feb 1, 2012 - Feb 2012
Acting Chief Executive Officer Microelectronics Laboratory College of Engineering & Computing University of South Carolina May 2009 - Apr 2011
1 Reasearch Associate Professor Intel Corporation May 2004 - Aug 2008
2 Senior Device Development Engineer Sensor Electronic Technology, Inc Mar 2001 - Apr 2004
3 Device Test Engineer and Manager For Semiconductor-Device-Characterizations, Radio-Frequencies

Education:

University of South Carolina 1999 - 2003
University of Idaho 1993 - 1996
Master of Science, Masters, Electrical Engineering, Electronics San Francisco State University 1990 - 1993
Bachelors, Bachelor of Science, Electrical Engineering University of South Carolina 1985 - 1987

Skills:

Cmos, Rf, R&D, Process Integration, Microelectronics, Photonics, Sensors, Semiconductors, Device Characterization, Electrical Engineering, Characterization, Spc, Design of Experiments, Optoelectronics

Languages:

English
French
Arabic

Ahmad Tarakji

Publications & IP owners

Us Patents

Approach To The Manufacturing Of Monolithic 3-Dimensional High-Rise Integrated-Circuits With Vertically-Stacked Double-Sided Fully-Depleted Silicon-On-Insulator Transistors

US Patent:

2018029, Oct 11, 2018

Filed:

Apr 11, 2017

Appl. No.:

15/731051

Inventors:

Ahmad Tarakji - Sacramento CA, US
Nirmal Chaudhary - Leesburg VA, US

International Classification:

H01L 27/12
H01L 23/00

Abstract:

Method to fabricate high-rise three-dimensional Integrated-Circuits (3D-ICs) is described. It has the major advantage over all the other known methods and prior arts to fabricate or manufacture 3D-ICs in that it substantially reduces RC-delays and fully eliminates or very substantially reduces the large and bulky electrically conductive Through-Silicon-VIAs in monolithic 3D integration. This enables the 3D-ICs to have faster operational speed with denser device integration.

Aluminum-Rich Field-Plated Nitride Transistors For Record High Currents

US Patent:

2018028, Oct 4, 2018

Filed:

Feb 13, 2017

Appl. No.:

15/530643

Inventors:

Ahmad Tarakji - Sacramento CA, US

International Classification:

H01L 29/778
H01L 29/20
H01L 21/02
H01L 29/66

Abstract:

New Nitride semiconductor epitaxy incorporating high Aluminum content is presented. It incorporated traces of Indium that adequately tuned its lattice size closer to that of a narrower bandgap semiconductor that interfaced it and formed a 2DEG device channel QW. The incorporation of adequate low molar fraction of Indium into AlN compound that possesses strong Spontaneous-Polarization enabled the lattice size of this epitaxy to better match that of the semiconductor interfacing it and did consequently grow thicker and induced very high carrier-concentrations into the device 2DEG QW resulting therefore in highest current densities.

Approach For An Area-Efficient And Scalable Cmos Performance Based On Advanced Silicon-On-Insulator (Soi), Silicon-On-Sapphire (Sos) And Silicon-On-Nothing (Son) Technologies

US Patent:

2017035, Dec 14, 2017

Filed:

Aug 18, 2017

Appl. No.:

15/731883

Inventors:

Ahmad Houssam Tarakji - Sacramento CA, US

International Classification:

H01L 29/786
H01L 27/12

Abstract:

The invention provides the guided design approach to optimize the device performance for a best area-efficient layout footprint in a single-leg MOS device that is based on any of the SOL SOS or SON technologies. The design methodology depends on new proprietaries device architectures that are also being claimed in this patent and that allow the implementations of the design equations in our methodology.

Approach For An Area-Efficient And Scalable Cmos Performance Based On Advanced Silicon-On-Insulator (Soi), Silicon-On-Sapphire (Sos) And Silicon-On-Nothing (Son) Technologies

US Patent:

2017004, Feb 9, 2017

Filed:

Aug 7, 2015

Appl. No.:

14/821685

Inventors:

Ahmad Tarakji - San Diego CA, US

International Classification:

H01L 29/786
H01L 29/78

Abstract:

The invention provides the guided design approach to optimize the device performance for a best area-efficient layout footprint in a single-leg MOS device that is based on any of the SOI, SOS or SON technologies. The design methodology depends on a new proprietary device architecture that is also being claimed in this patent and that allows the implementations of the design equations of our methodology.

Possible Relatives

Ahmad V Johnson Ahmad D Jones Ahmad J Lee Ahmad J Lewis Ahmad J Martin Ahmad R Williams Ahmad R Mohammad Ahmad Y Thomas Ahmad A Najafi Ahmad Nasser

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