Akshay Nareshraj Singh, Age 4710101 W Raleigh St, Boise, ID 83709
Akshay Singh Phones & Addresses
10101 W Raleigh St, Boise, ID 83709 (479) 871-3745
Kenner, LA
Palo Alto, CA
3550 Nicholson Dr, Baton Rouge, LA 70802 (225) 338-0974 (225) 346-0486
College Station, TX
Chicago, IL
Mentions for Akshay Nareshraj Singh
Publications & IP owners
Us Patents
Bond Pads For Semiconductor Die Assemblies And Associated Methods And Systems
US Patent:
2023004, Feb 16, 2023
Filed:
Feb 7, 2022
Appl. No.:
17/666437
Inventors:
- Boise ID, US
Akshay N. Singh - Boise ID, US
Keizo Kawakita - Hiroshima, JP
Bret K. Street - Meridian ID, US
Akshay N. Singh - Boise ID, US
Keizo Kawakita - Hiroshima, JP
Bret K. Street - Meridian ID, US
International Classification:
H01L 23/00
H01L 25/065
H01L 25/065
Abstract:
Bond pads for semiconductor die assemblies, and associated methods and systems are disclosed. In one embodiment, a semiconductor die assembly includes a first semiconductor die including a first bond pad on a first side of the first semiconductor die. The semiconductor die assembly further includes a second semiconductor die including a second bond pad on a second side of the second semiconductor die. The first bond pad is aligned and bonded to the second bond pad at a bonding interface between the first and second bond pads, and at least one of the first and second bond pads include a first metal and a second metal different than the first metal. Further, the first metal is located at the bonding interface and the second metal has a first thickness corresponding to at least one-fourth of a second thickness of the first or second bond pad.
High Density Pillar Interconnect Conversion With Stack To Substrate Connection
US Patent:
2021035, Nov 11, 2021
Filed:
Jul 22, 2021
Appl. No.:
17/383304
Inventors:
- Boise ID, US
Kyle K. Kirby - Eagle ID, US
Akshay N. Singh - Boise ID, US
Kyle K. Kirby - Eagle ID, US
Akshay N. Singh - Boise ID, US
International Classification:
H01L 25/065
H01L 23/498
H01L 21/56
H01L 23/31
H01L 23/498
H01L 21/56
H01L 23/31
Abstract:
A semiconductor device assembly can include a first semiconductor device and an interposer. The interposer can include a substrate and through vias in which individual vias include an exposed portion and an embedded portion, the exposed portions projecting from one or both of the first surface and the second surface of the substrate, and the embedded portions extending through at least a portion of the substrate. The interposer can include one or more test pads, a first electrical contact, and a second electrical contact. The semiconductor device assembly can include a controller positioned on an opposite side of the interposer from the first semiconductor device and operably coupled to the interposer via connection to the second electrical contact.
High Density Pillar Interconnect Conversion With Stack To Substrate Connection
US Patent:
2021022, Jul 22, 2021
Filed:
Apr 2, 2021
Appl. No.:
17/221537
Inventors:
- Boise ID, US
Kyle K. Kirby - Eagle ID, US
Akshay N. Singh - Boise ID, US
Kyle K. Kirby - Eagle ID, US
Akshay N. Singh - Boise ID, US
International Classification:
H01L 23/538
H01L 23/498
H01L 23/00
H01L 21/48
H01L 25/065
H01L 23/498
H01L 23/00
H01L 21/48
H01L 25/065
Abstract:
A semiconductor device assembly can include a semiconductor device having a substrate and vias electrically connected to circuitry of the semiconductor device. Individual vias can have an embedded portion extending from the first side to the second side of the substrate and an exposed portion projecting from the second side of the substrate. The assembly can include a density-conversion connector comprising a connector substrate and a first array of contacts formed at the first side thereof, the first array of contacts occupying a first footprint area on the first side thereof, and wherein individual contacts of the first array are electrically connected to the exposed portion of a corresponding via of the semiconductor device. The assembly can include a second array of contacts electrically connected to the first array, formed at the second side of the connector substrate, and occupying a second footprint area larger than the first footprint area.
High Density Pillar Interconnect Conversion With Stack To Substrate Connection
US Patent:
2021013, May 6, 2021
Filed:
Nov 1, 2019
Appl. No.:
16/671558
Inventors:
- Boise ID, US
Kyle K. Kirby - Eagle ID, US
Akshay N. Singh - Boise ID, US
Kyle K. Kirby - Eagle ID, US
Akshay N. Singh - Boise ID, US
International Classification:
H01L 23/538
H01L 25/065
H01L 23/498
H01L 23/00
H01L 21/48
H01L 25/065
H01L 23/498
H01L 23/00
H01L 21/48
Abstract:
A semiconductor device assembly can include a semiconductor device having a substrate and vias electrically connected to circuitry of the semiconductor device. Individual vias can have an embedded portion extending from the first side to the second side of the substrate and an exposed portion projecting from the second side of the substrate. The assembly can include a density-conversion connector comprising a connector substrate and a first array of contacts formed at the first side thereof, the first array of contacts occupying a first footprint area on the first side thereof, and wherein individual contacts of the first array are electrically connected to the exposed portion of a corresponding via of the semiconductor device. The assembly can include a second array of contacts electrically connected to the first array, formed at the second side of the connector substrate, and occupying a second footprint area larger than the first footprint area.
High Density Pillar Interconnect Conversion With Stack To Substrate Connection
US Patent:
2021013, May 6, 2021
Filed:
Nov 1, 2019
Appl. No.:
16/671546
Inventors:
- Boise ID, US
Kyle K. Kirby - Eagle ID, US
Akshay N. Singh - Boise ID, US
Kyle K. Kirby - Eagle ID, US
Akshay N. Singh - Boise ID, US
International Classification:
H01L 25/065
H01L 23/498
H01L 23/31
H01L 21/56
H01L 23/498
H01L 23/31
H01L 21/56
Abstract:
A semiconductor device assembly can include a first semiconductor device and an interposer. The interposer can include a substrate and through vias in which individual vias include an exposed portion and an embedded portion, the exposed portions projecting from one or both of the first surface and the second surface of the substrate, and the embedded portions extending through at least a portion of the substrate. The interposer can include one or more test pads, a first electrical contact, and a second electrical contact. The semiconductor device assembly can include a controller positioned on an opposite side of the interposer from the first semiconductor device and operably coupled to the interposer via connection to the second electrical contact.
Semiconductor Device Assemblies Including Multiple Shingled Stacks Of Semiconductor Dies
US Patent:
2020002, Jan 16, 2020
Filed:
Sep 23, 2019
Appl. No.:
16/578592
Inventors:
- Boise ID, US
Akshay N. Singh - Boise ID, US
Akshay N. Singh - Boise ID, US
International Classification:
H01L 25/065
H01L 25/00
H01L 23/00
H01L 23/50
H01L 25/00
H01L 23/00
H01L 23/50
Abstract:
A semiconductor device assembly includes a substrate having a plurality of external connections, a first shingled stack of semiconductor dies disposed directly over a first location on the substrate and electrically coupled to a first subset of the plurality of external connections, and a second shingled stack of semiconductor dies disposed directly over a second location on the substrate and electrically coupled to a second subset of the plurality of external connections. The semiconductor device assembly further includes an encapsulant at least partially encapsulating the substrate, the first shingled stack and the second shingled stack.
Semiconductor Device Assembly With Pillar Array
US Patent:
2019034, Nov 7, 2019
Filed:
Jul 16, 2019
Appl. No.:
16/513466
Inventors:
- Boise ID, US
Akshay N. Singh - Boise ID, US
Kyle K. Kirby - Eagle ID, US
Akshay N. Singh - Boise ID, US
Kyle K. Kirby - Eagle ID, US
International Classification:
H01L 21/48
H01L 25/065
H01L 21/66
H01L 23/498
H01L 23/48
H01L 25/065
H01L 21/66
H01L 23/498
H01L 23/48
Abstract:
A semiconductor device assembly and method of forming a semiconductor device assembly that includes a first substrate, a second substrate disposed over the first substrate, at least one interconnect between the substrates, and at least one pillar extending from the bottom surface of the first substrate. The pillar is electrically connected to the interconnect and is located adjacent to a side of the first substrate. The pillar is formed by filling a via through the substrate with a conductive material. The first substrate may include an array of pillars extending from the bottom surface adjacent to a side of the substrate that are formed from a plurality of filled vias. The substrate may include a test pad located on the bottom surface or located on the top surface. The pillars may include a removable coating enabling the pillars to be probed without damaging the inner conductive portion of the pillar.
Semiconductor Device Assemblies Including Multiple Shingled Stacks Of Semiconductor Dies
US Patent:
2019024, Aug 8, 2019
Filed:
Apr 15, 2019
Appl. No.:
16/383903
Inventors:
- Boise ID, US
Akshay N. Singh - Boise ID, US
Akshay N. Singh - Boise ID, US
International Classification:
H01L 25/065
H01L 23/00
H01L 25/00
H01L 23/50
H01L 23/00
H01L 25/00
H01L 23/50
Abstract:
A semiconductor device assembly includes a substrate having a plurality of external connections, a first shingled stack of semiconductor dies disposed directly over a first location on the substrate and electrically coupled to a first subset of the plurality of external connections, and a second shingled stack of semiconductor dies disposed directly over a second location on the substrate and electrically coupled to a second subset of the plurality of external connections. The semiconductor device assembly further includes an encapsulant at least partially encapsulating the substrate, the first shingled stack and the second shingled stack.
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