Albert J Weidner, Age 78Phoenix, AZ

5301292, Apr 5, 1994

Feb 22, 1991

7/659796

William K. Hilton - Phoenix AZ
Albert J. Weidner - Tempe AZ

VLSI Technology, Inc. - San Jose CA

G06F 1200

395425

Apparatus for decoding and comparing memory addresses which determines DRAM size and interleave options utilized is disclosed. A row address and bank select bits are decoded and latched and are subsequently compared with the address during the next memory cycle. If the next address matches the address stored in the latch, a "page hit" occurs and the memory cycle is shortened since the addresses during the consecutive memory address will differ only in the column address.

4373182, Feb 8, 1983

Aug 19, 1980

6/179514

Gary E. Schultz - San Juan Capistrano CA
Albert J. Weidner - Tempe AZ

Sperry Corporation - New York NY

G06F 936

364200

This invention relates to a system for determining an effective address based upon a calculation performed on address information. Depending upon the result of the calculation firmware or hardware will control further operation of the system.

4419726, Dec 6, 1983

Jan 16, 1981

6/225701

Albert J. Weidner - Tempe AZ

Sperry Corporation - New York NY

G06F 936
G06F 942

364200

An instruction decoding system for data processing apparatus in which alternative instruction interpretations are made possible through hardware sensing of the operational state of one or more machine elements. In one embodiment, a zero detect unit is used to sense the state of a subroutine stack used in a microprogrammed system, therefore permitting a generic "exit" microcommand to be interpreted either as a "return" or a "decode" depending upon the state of the subroutine stack.

5719510, Feb 17, 1998

Mar 27, 1996

8/622375

Albert Weidner - Tempe AZ

Intel Corporation - Santa Clara CA

H03B 1900

327119

The clock generator generates an output clock signal of known frequency from an internally generated high frequency signal of unknown frequency and from a low frequency input signal of known frequency. To this end, the clock multiplier first determines the frequency of the internal clock signal from a comparison with the input clock signal. In one arrangement, the frequency of the internal signal is determined by counting a number of clock transitions occurring during the internal signal within one period of the input clock signal. Once the frequency of the internal signal has been determined, the clock multiplier generates an output clock signal based upon the internal clock signal but adjusted in accordance with the newly determined frequency of the internal clock signal. In one arrangement, the clock multiplier employs a programmable divider. A software control unit calculates a divide factor for use by the programmable divider based upon the period of the input signal, the count of transitions, and the desired period for the output signal.