Amar Amin resumes & CV records
Resumes
Amar J Amin, Age 421001 Main St, Milpitas, CA 95035
Amar Amin Phones & Addresses
1001 Main St, Milpitas, CA 95035 (408) 957-0329
Augusta, GA
Fremont, CA
Atlanta, GA
Norcross, GA
Charlotte, NC
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Amar J Amin
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Mentions for Amar J Amin
Publications & IP owners
Us Patents
Wire Bond Integrated Circuit Package For High Speed I/O
US Patent:
7804167, Sep 28, 2010
Filed:
Dec 1, 2006
Appl. No.:
11/565701
Inventors:
Clifford Fishley - San Jose CA, US
Abiola Awujoola - Pleasanton CA, US
Leonard Mora - San Jose CA, US
Amar Amin - Milpitas CA, US
Maurice Othieno - Union City CA, US
Chok J. Chia - Cupertino CA, US
Abiola Awujoola - Pleasanton CA, US
Leonard Mora - San Jose CA, US
Amar Amin - Milpitas CA, US
Maurice Othieno - Union City CA, US
Chok J. Chia - Cupertino CA, US
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
H01L 23/528
H01L 21/768
H01L 21/768
US Classification:
257691, 257786, 257692, 257784, 257782, 257E23079, 257E23153, 257E21575, 438666, 438612, 438622
Abstract:
An integrated circuit package includes a package substrate, a die attach pad formed on the package substrate for securing a die to the package substrate, a ground bonding ring formed on the package substrate for attaching core and I/O ground bond wires between the die and the package substrate, and a first plurality of bond fingers formed immediately adjacent to the ground bonding ring for attaching a first set of I/O signal bond wires between the package substrate and the die.
Device For Avoiding Parasitic Capacitance In An Integrated Circuit Package
US Patent:
8049340, Nov 1, 2011
Filed:
Mar 22, 2006
Appl. No.:
11/277188
Inventors:
Jeffrey Hall - San Jose CA, US
Shawn Nikoukary - Santa Clara CA, US
Amar Amin - Milpitas CA, US
Michael Jenkins - San Jose CA, US
Shawn Nikoukary - Santa Clara CA, US
Amar Amin - Milpitas CA, US
Michael Jenkins - San Jose CA, US
Assignee:
LSI Corporation - Milpitas CA
International Classification:
H01L 23/48
US Classification:
257777, 257E23019, 257E23151, 257758
Abstract:
An integrated circuit package substrate includes a first and an additional electrically conductive layer separated from each other by an electrically insulating layer, a contact pad formed in the first electrically conductive layer for making a direct connection between the integrated circuit package substrate and a printed circuit board, and a cutout formed in the additional electrically conductive layer wherein the cutout encloses an area that completely surrounds the contact pad for avoiding parasitic capacitance between the additional electrically conductive layer and the printed circuit board.
Semiconductor Package And Method Using Isolated Vplane To Accommodate High Speed Circuitry Ground Isolation
US Patent:
8129759, Mar 6, 2012
Filed:
Nov 24, 2009
Appl. No.:
12/625457
Inventors:
Maurice O. Othieno - Union City CA, US
Chok J. Chia - Cupertino CA, US
Amar J. Amin - Milpitas CA, US
Chok J. Chia - Cupertino CA, US
Amar J. Amin - Milpitas CA, US
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
H01L 23/52
US Classification:
257207, 257208, 257211, 257691, 257E23079, 257E23153
Abstract:
Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate which can have an integrated circuit die attached thereto. The package includes a dedicated high-speed ground plane that is electrically isolated from the ground plane used to ground the low speed circuitry of the package.
Methods For Avoiding Parasitic Capacitance In An Integrated Circuit Package
US Patent:
8288269, Oct 16, 2012
Filed:
Oct 4, 2011
Appl. No.:
13/252632
Inventors:
Jeffrey Hall - San Jose CA, US
Shawn Nikoukary - Santa Clara CA, US
Amar Amin - Milpitas CA, US
Michael Jenkins - San Jose CA, US
Shawn Nikoukary - Santa Clara CA, US
Amar Amin - Milpitas CA, US
Michael Jenkins - San Jose CA, US
Assignee:
LSI Corporation - Milpitas CA
International Classification:
H01L 21/4763
US Classification:
438622, 257758, 257E21536
Abstract:
An integrated circuit package substrate includes a first and an additional electrically conductive layer separated from each other by an electrically insulating layer, a contact pad formed in the first electrically conductive layer for making a direct connection between the integrated circuit package substrate and a printed circuit board, and a cutout formed in the additional electrically conductive layer wherein the cutout encloses an area that completely surrounds the contact pad for avoiding parasitic capacitance between the additional electrically conductive layer and the printed circuit board.
Semiconductor Package And Method Using Isolated Vss Plane To Accommodate High Speed Circuitry Ground Isolation
US Patent:
2007023, Oct 11, 2007
Filed:
Apr 6, 2006
Appl. No.:
11/399723
Inventors:
Maurice Othieno - Union City CA, US
Chok Chia - Cupertino CA, US
Amar Amin - Milpitas CA, US
Chok Chia - Cupertino CA, US
Amar Amin - Milpitas CA, US
International Classification:
H01L 23/02
US Classification:
257678000
Abstract:
Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate which can have an integrated circuit die attached thereto. The package includes a dedicated high-speed ground plane that is electrically isolated from the ground plane used to ground the low speed circuitry of the package.
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