Amitabh Jain, Age 55Oviedo, FL
Amitabh Jain Phones & Addresses
Oviedo, FL
Round Rock, TX
4225 1St St, Tucson, AZ 85719 (520) 408-8072
819 N 1St Ave APT 109, Tucson, AZ 85719
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Us Patents
Ultra-Shallow Arsenic Junction Formation In Silicon Germanium
US Patent:
7163878, Jan 16, 2007
Filed:
Nov 4, 2005
Appl. No.:
11/267413
Inventors:
Puneet Kohli - Austin TX, US
Mark Rodder - University Park TX, US
Rick Wise - Fairview TX, US
Amitabh Jain - Allen TX, US
Mark Rodder - University Park TX, US
Rick Wise - Fairview TX, US
Amitabh Jain - Allen TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 21/265
US Classification:
438520, 257E21343
Abstract:
In one aspect, the present invention provides a method of forming junctions in a silicon-germanium layer (). In this particular embodiment, the method comprises implanting a dopant () into the silicon-germanium layer () and implanting fluorine () into the silicon-germanium layer ().
N-Type Semiconductor Component With Improved Dopant Implantation Profile And Method Of Forming Same
US Patent:
2008026, Oct 30, 2008
Filed:
Apr 25, 2007
Appl. No.:
11/739965
Inventors:
Puneet Kohli - Austin TX, US
Manoj Mehrotra - Plano TX, US
Antonio Luis Pacheco Rotondaro - Dallas TX, US
Stan Ashburn - McKinney TX, US
Nandakumar Mahalingam - Richardson TX, US
Amitabh Jain - Allen TX, US
Manoj Mehrotra - Plano TX, US
Antonio Luis Pacheco Rotondaro - Dallas TX, US
Stan Ashburn - McKinney TX, US
Nandakumar Mahalingam - Richardson TX, US
Amitabh Jain - Allen TX, US
International Classification:
H01L 21/425
H01L 29/00
H01L 21/22
H01L 29/00
H01L 21/22
US Classification:
438542, 257607, 438511, 257E21473, 257E29001, 257288
Abstract:
The disclosure relates to a method of forming an n-type doped active area on a semiconductor substrate that presents an improved placement profile. The method comprises the placement of arsenic in the presence of a carbon-containing arsenic diffusion suppressant in order to reduce the diffusion of the arsenic out of the target area during heat-induced annealing. The method may additionally include the placement of an amorphizer, such as germanium, in the target area in order to reduce channeling of the arsenic ions through the crystalline lattice. The method may also include the use of arsenic in addition to another n-type dopant, e.g. phosphorus, in order to offset some of the disadvantages of a pure arsenic dopant. The disclosure also relates to a semiconductor component, e.g. an NMOS transistor, formed in accordance with the described methods.
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