Andrew David Bianchi, Age 5349 Craig Rd, Hillsdale, NJ 07642

7099201, Aug 29, 2006

Feb 10, 2005

11/055043

Andrew James Bianchi - Austin TX, US
Yuen Hung Chan - Poughkeepsie NY, US
William Vincent Huott - Holmes NY, US
Michael Ju Hyeok Lee - Austin TX, US
Edelmar Seewann - Austin TX, US

International Business Machines Corporation - Armonk NY

G11C 7/10

36518905, 36518508, 36523008

An apparatus and method is provided that combines both self test and functional features in a single latch circuit, which may be used with an SRAM array and is usefully embodied as an L1-L2 latch. During partial writes from an SRAM array, data bits of unknown state are inhibited from entering the latch circuit, while data for testing is allowed to enter. In one useful embodiment of the invention the latch circuit is used with a mode control that provides mode select signals to operate the latch circuit in one of a plurality of modes, including at least full write and partial write modes. The latch circuit further includes a data hold circuit for selectively receiving and storing data coupled to the latch circuit. A first enabling circuit responsive to the mode select signals enables the hold circuit to receive all the data contained in the array during a full write mode, and further enables the hold circuit to receive only some of the data bits contained in the array during a partial write mode.

7466647, Dec 16, 2008

Feb 9, 2005

11/054287

Andrew James Bianchi - Austin TX, US
Eric Jason Fluhr - Round Rock TX, US
Masood Ahmed Khan - Cedar Park TX, US
Michael Ju Hyeok Lee - Austin TX, US
Edelmar Seewann - Austin TX, US

International Business Machines Corporation - Armonk NY

G01R 31/08
G06F 13/28
G06F 12/00
G06F 9/26

370222, 370535, 710 23, 711138, 711207

A method and apparatus for using a 2:1 MUX to control read access, data bypass, and page size bypass in a memory array. The mechanism of the present invention reduces the 3:1 MUX normally required to manage these three functions to a 2:1 MUX.

7471103, Dec 30, 2008

Dec 6, 2006

11/567581

Andrew James Bianchi - Austin TX, US
Jose Angel Paredes - Austin TX, US

International Business Machines Corporation - Armonk NY

G06F 7/38
H03K 19/173

326 38, 326 37

A logic gate is described that implements complex logic within a memory array. The logic gate receives at least three of a first storage cell signal, a second storage cell signal, a first external signal, or a second external signal at a first input circuitry and second input circuitry. The logic gate then performs one of a set of logic functions using the first storage cell signal, the second storage cell signal, the first external signal, or the second external signal. The set of logic functions includes at least one of a matching function, an OR-AND function, or an AND function.

7683662, Mar 23, 2010

Oct 14, 2008

12/250917

Andrew James Bianchi - Austin TX, US
Jose Angel Paredes - Austin TX, US

International Business Machines Corporation - Armonk NY

G06F 7/31
H03K 19/173

326 38, 326 37

A logic gate is described that implements complex logic within a memory array. The logic gate receives at least three of a first storage cell signal, a second storage cell signal, a first external signal, or a second external signal at a first input circuitry and second input circuitry. The logic gate then performs one of a set of logic functions using the first storage cell signal, the second storage cell signal, the first external signal, or the second external signal. The set of logic functions includes at least one of a matching function, an OR-AND function, or an AND function.

2004022, Nov 4, 2004

Apr 30, 2003

10/427135

Andrew Bianchi - Austin TX, US
Jose Paredes - Austin TX, US

INTERNATIONAL BUSINESS MACHINES CORP. - Armonk NY

G06F012/08

711/131000, 711/136000

An apparatus for implementing a least-recently used (LRU) mechanism in a multi-port cache memory includes an LRU array and a shift decoder. The LRU array has multiple entries. The shift decoder includes a shifting means for shifting the entries within the LRU array. The shifting means shifts a current one of the entries and adjacent entries once, and loading new address, in response to a single cache hit in the current one of the entries. The shifting means shifts a current one of the entries and adjacent entries once, and loading an address of only one of multiple requesters into the most-recently used (MRU) entry, in response to multiple cache hits in the current one of the entries. The shifting means shifts all subsequent entries, including the current entries, n times, and loading addresses of all requesters contributed to the multiple cache hits in consecutive entries into the MRU entry and subsequent entries, in response to multiple cache hits in consecutive entries. The shifting means shifts some of the entries n times, some of the entries n-1 times, etc., and loading addresses of all requesters that have a cache hit in the multiple cache hits into the MRU entry and subsequent entries, in response to multiple cache hits not in the same entry or consecutive entries.