Andrew C Felch, Age 452351 Oberlin St, Palo Alto, CA 94306

8516280, Aug 20, 2013

Jun 11, 2012

13/493515

Andrew C. Felch - Hanover NH, US
Richard H. Granger - Lebanon NH, US

Cognitive Electronics, Inc. - Boston MA

G06F 1/00
G06F 13/00

713300, 711100

A computing system is provided that includes a web page search node including a web page collection, a web server, and a search page returner.

8588555, Nov 19, 2013

Jun 11, 2010

12/814369

Andrew C. Felch - Hanover NH, US
Richard H. Granger - Lebanon NH, US

Cognitive Electronics, Inc. - Lebanon NH

G06K 9/54
G06K 9/48
G06F 15/76

382304, 382199, 712 30

This invention provides a computer processor architecture optimized for power-efficient computation of certain sensory recognition (e. g. vision) algorithms on a single computer chip. Illustratively, the architecture is optimized to carry out low-level routines and a special class of high-level sensory recognition routines derived from research into human brain perception processes. In an illustrative embodiment, the processor includes a plurality of processing nodes, arranged in a hierarchy of layers, and the processor resolves features from sensory information input and provides the feature information as input to a lowest hierarchy layer thereof. The hierarchy simultaneously, recognizes multiple components of the features, which are transferred between the layers so as to build likely recognition candidates. Each node can further include memory constructed and arranged to refresh and retain features determined to be likely recognition candidates by a thresholding process. These are provided to an overseer that directs a function to occur.

8209597, Jun 26, 2012

Mar 22, 2010

12/728498

Andrew C. Felch - Hanover NH, US
Richard H. Granger - Lebanon NH, US

Cognitive Electronics, Inc. - Lebanon NH

G06F 7/02

714820, 714822

This invention provides a system and method that can employ a low-instruction-per-second (lower-power), highly parallel processor architecture to perform the low-precision computations. These are aggregated at high-precision by an aggregator. Either a high-precision processor arrangement, or a low-precision processor arrangement, employing soft-ware-based high-precision program instructions performs the less-frequent, generally slower high-precision computations of the aggregated, more-frequent low-precision computations. One final aggregator totals all low-precision computations and another high-precision aggregator totals all high-precision computations. An equal number of low precision computations are used to generate the error value that is subtracted from the low-precision average. A plurality of lower-power processors can be arrayed to provide the low-precision computation function. Alternatively a plurality of SIMD can be used to alternately conduct low-precision computations for a predetermined number of operations and high-precision operations on a fewer number of operations.

2009008, Mar 26, 2009

Sep 23, 2008

12/236187

Andrew C. Felch - Hanover NH, US
Richard H. Granger - Lebanon NH, US

COGNITIVE ELECTRONICS, INC. - Lebanon NH

G06F 17/30
G06F 1/26
G06F 9/455

707 5, 707 3, 713300, 703 23, 707E17108, 707E17109

This invention provides a computer system architecture and method for providing the same which can include a web page search node including a web page collection. The system and method can also include a web server configured to receive, from a given user via a web browser, a search query including keywords. The node is caused to search pages in its own collection that best match the search query. A search page returner may be provided which is configured to return, to the user, high ranked pages. The node may include a power-efficiency-enhanced processing subsystem, which includes M processors. The M processors are configured to emulate N virtual processors, and they are configured to limit a virtual processor memory access rate at which each of the N virtual processors accesses memory. The memory accessed by each of the N virtual processors may be RAM. In select embodiments, the memory accessed by each of the N virtual processors includes DRAM having a high capacity yet lower power consumption then SRAM.

2013005, Feb 28, 2013

Aug 24, 2012

13/594166

Andrew C. FELCH - Palo Alto CA, US

COGNITIVE ELECTRONICS, INC. - Lebanon NH

G06F 17/10

708517

An automated method of performing exponentiation is disclosed. A plurality of tables holding factors for obtaining results of Exponentiations are provided. The plurality of tables are loaded into computer memory. Each factor is the result of a second exponentiation of a constant and an exponent. The exponent is related to a memory address corresponding to the factor. A plurality of memory addresses are identified for performing the first exponentiation by breaking up the first exponentiation into equations, the results of which are factors of the first Exponentiation. The exponents of the equations are related to the memory addresses corresponding to the factors held in the tables. A plurality of lookups into the computer memory are performed to retrieve the factors held in the tables corresponding to the respective memory addresses. The retrieved factors are multiplied together to obtain the result of the first exponentiation.

2013005, Feb 28, 2013

Aug 24, 2012

13/594181

Andrew C. FELCH - Palo Alto CA, US

COGNITIVE ELECTRONICS, INC. - Lebanon NH

G06F 15/76

712 42, 712E09002

An integrated circuit (IC) is disclosed. The integrated circuit includes a non-reconfigurable multi-threaded processor core that implements a pipeline having n ordered stages, wherein n is an integer greater than 1. The multi-threaded processor core implements a default instruction set. The integrated circuit also includes reconfigurable hardware that implements n discrete pipeline stages of a reconfigurable execution unit. The n discrete pipeline stages of the reconfigurable execution unit are pipeline stages of the pipeline that is implemented by the multi-threaded processor core.

2013006, Mar 7, 2013

Aug 24, 2012

13/594125

Andrew C. FELCH - Palo Alto CA, US

COGNITIVE ELECTRONICS, INC. - Lebanon NH

G06F 9/45

717149

An automated method of optimizing execution of a program in a parallel processing environment is described. The program is adapted to execute in data memory and instruction memory. An optimizer receives the program to be optimized. The optimizer instructs the program to be compiled and executed. The optimizer observes execution of the program and identifies a subset of instructions that execute most often. The optimizer also identifies groups of instructions associated with the subset of instructions that execute most often. The identified groups of instructions include the identified subset of instructions that execute most often. The optimizer recompiles the program and stores the identified groups of instructions in instruction memory. The remaining instructions portions of the program are stored in the data memory. The instruction memory has a higher access rate and smaller capacity than the data memory. Once recompiled, subsequent execution of the program occurs using the recompiled program.

2013006, Mar 7, 2013

Aug 24, 2012

13/594207

Andrew C. FELCH - Palo Alto CA, US

COGNITIVE ELECTRONICS, INC. - Lebanon NH

G06F 21/20

726 4, 726 3

A method of providing network security for executing applications is disclosed. One or more servers including a plurality of microprocessors and a plurality of network processors are provided. A first grouping of microprocessors executes a first application. The first application is executed using the microprocessors in the first grouping. The microprocessors in the first grouping of microprocessors are permitted to communicate with each other via one or more of the network processors. A second grouping of microprocessors executes a second application. At least one server has one or more microprocessors for executing the first application and one or more different microprocessors for executing the second application. The second application is executed using the microprocessors in the second grouping of microprocessors. One or more of the network processors prevent the microprocessors in the first grouping from communicating with the microprocessors in the second grouping during periods of simultaneous execution.