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Andrew M Jennings, Age 39Chattanooga, TN

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Known as:
Andrew Jennings Grisham Grisham Andrew Jennings Andrew M
Related to:
William E Jennings 94

Andrew Jennings Phones & Addresses

Chattanooga, TN

Wheaton, IL

Minneapolis, MN

3636 Cedar Ave S #2, Minneapolis, MN 55407 (612) 245-5053

Work

Company: Sofa king juicy burger - Red Bank, TN Apr 2013 Position: Team member

Education

School / High School: University of Tennessee at Chattanooga- Chattanooga, TN 2012 Specialities: Music

Skills

Verbal and Written Communication • Computer Proficient • Problem Solving • Leadership • Quick Thinking • Functions well within a team or solo.

Mentions for Andrew M Jennings

Career records & work history

Lawyers & Attorneys

Andrew Jennings Photo 1

Andrew Jennings - Lawyer

Office:
Ince & Co.
ISLN:
921538408
Andrew Jennings Photo 2

Andrew Jennings - Lawyer

Specialties:
Criminal Law (Prosecution)
ISLN:
923328410
Admitted:
2012

Medicine Doctors

Andrew Jennings

Specialties:
Traumatic Surgery
Work:
Urgent Surgery Associates
2710 Swiss Ave, Dallas, TX 75204
(214) 821-1599 (phone) (214) 821-8985 (fax)
Site
Education:
Medical School
University of Texas Southwestern Medical Center at Dallas
Graduated: 2008
Procedures:
Small Bowel Resection
Conditions:
Appendicitis, Intestinal Obstruction, Abdominal Hernia, Cholelethiasis or Cholecystitis, Gastrointestinal Hemorrhage, Inguinal Hernia, Ischemic Bowel Disease, Thoracid Aortic Aneurysm, Ventral Hernia
Languages:
English, Spanish
Description:
Dr. Jennings graduated from the University of Texas Southwestern Medical Center at Dallas in 2008. He works in Dallas, TX and specializes in Traumatic Surgery. Dr. Jennings is affiliated with Baylor Scott & White Medical Center Waxahachie.
Andrew Jennings Photo 3

Andrew Jennings

License Records

Andrew Michael Jennings

Licenses:
License #: E-11942 - Expired
Category: Engineering Intern

Andrew C Jennings

Licenses:
License #: 33577 - Expired
Category: Tow Truck Operator (Incident Management)
Expiration Date: Jan 28, 2016

Andrew Jennings resumes & CV records

Resumes

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Andrew Jennings

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Andrew Jennings

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Andrew Jennings

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Andrew Jennings

Location:
United States
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Data Center Operations Manager

Position:
Data Center Operations Manager at Rackspace Hosting
Location:
San Antonio, Texas
Industry:
Information Technology and Services
Work:
Rackspace Hosting - Greater Chicago Area since Nov 2009
Data Center Operations Manager

Publications & IP owners

Us Patents

System And Method For Synchronizing Memory Management Functions Of Two Disparate Operating Systems

US Patent:
2008015, Jun 26, 2008
Filed:
Dec 21, 2006
Appl. No.:
11/643422
Inventors:
Andrew T. Jennings - Minneapolis MN, US
Feng-Jung Kao - Minneapolis MN, US
Kerry M. Langsford - Roseville MN, US
Michael J. Rieschl - Cottage Glove MN, US
David W. Schroth - Minneapolis MN, US
International Classification:
G06F 15/177
G06F 12/02
US Classification:
713 2, 711E12002
Abstract:
A memory management interface is provided to synchronize the operation of two disparate operating systems (OSes) that are executing on the same data processing platform. In one embodiment, the first operating system is a legacy OS of the type that is generally associated with an enterprise-level data processing system such as a mainframe. In contrast, the second OS is of a type designed to execute on commodity hardware such as personal computers. The first OS communicates with the second OS via a control logic interface to establish its execution environment, and to perform memory management functions. This interface supports a two-phase boot process that ensures that all memory allocated to the first OS can be released if an error occurs that affects operations of the first OS. This prevents the development of memory leaks.

Stablizing Operation Of An Emulated System

US Patent:
2009027, Nov 5, 2009
Filed:
May 2, 2008
Appl. No.:
12/114233
Inventors:
Andrew T. Jennings - Minneapolis MN, US
Michael J. Rieschl - St. Paul MN, US
David W. Schroth - Minneapolis MN, US
International Classification:
G06F 9/455
US Classification:
703 26
Abstract:
Disclosure of approaches for stabilizing an emulated system. In one approach, a first operating system (OS) is executed on an instruction processor, the first OS including instructions native to the instruction processor. A second OS and a plurality of application programs are emulated on the first OS. The second OS polls the first OS for memory statistics of the first OS. The memory statistics indicate a current state of operating parameters of the memory of the data processing system used by the first OS in managing the data processing system. The second OS controls a number of the application programs allowed to execute in response to the memory statistics provided by the first OS to the second OS.

System And Method For Affinity Dispatching For Task Management In An Emulated Multiprocessor Environment

US Patent:
2012007, Mar 22, 2012
Filed:
Sep 21, 2010
Appl. No.:
12/886969
Inventors:
David W. Schroth - Minneapolis MN, US
Brian Garrett - Salt Lake City UT, US
Andrew T. Jennings - Minnetonka MN, US
Michael John Rieschi - St. Paul MN, US
International Classification:
G06F 9/46
US Classification:
718 1
Abstract:
The disclosure relates generally to managing assignment of tasks among instruction processors (IPs) within a computer system having multiple IPs, and more particularly to binding emulated IPs with a host system's IPs (e.g., processor cores) for facilitating control over affinity-based assignment of tasks among the host system's IPs by a task manager (e.g., OS) that is executing on the emulated IPs, rather than running directly on the host system's IPs. Certain embodiments provide techniques for binding emulated IPs with actual IPs of a computing system that is hosting the emulated IPs, thereby enabling better control of management of the system by a task manager executing on the emulated IPs. For instance, in certain embodiments, a dispatcher (e.g., of an OS running on emulated IPs) performs affinity-based management of task assignment for tasks performed for an application program among IPs of a host system that is hosting the emulated IPs.

Just-In-Time Dynamic Translation For Translation, Compilation, And Execution Of Non-Native Instructions

US Patent:
2015027, Oct 1, 2015
Filed:
Dec 30, 2013
Appl. No.:
14/143285
Inventors:
ANDREW T. JENNINGS - MINNETONKA MN, US
Charles R. Caldarale - Roseville MN, US
Kevin W. Harris - Roseville MN, US
MAURICE MARKS - ROSEVILLE MN, US
Assignee:
Unisys Corporation - Blue Bell PA
International Classification:
G06F 9/45
G06F 9/455
Abstract:
A method for executing non-native instructions in a computing system having a processor configured to execute native instructions may include fetching a first non-native instruction from a plurality of non-native instructions; interpreting the first non-native instruction to generate a first instruction code; compiling the first instruction code to generate a first native instruction corresponding to the first non-native instruction; determining whether to execute the first instruction code or the generated first native instruction; and implementing a first virtual machine instruction corresponding to the first non-native instruction based, at least in part, on determining whether to execute the first instruction code or the first native instruction.

Dynamic On/Off Just-In-Time Compilation In A Dynamic Translator Using Instruction Code Translation

US Patent:
2015018, Jul 2, 2015
Filed:
Dec 30, 2013
Appl. No.:
14/143297
Inventors:
Andrew T. Jennings - Minnetonka MN, US
Charles R. Caldarale - Roseville MN, US
Gregory Heimann - Roseville MN, US
Maurice Marks - Roseville MN, US
Kevin Harris - Nashua NH, US
Assignee:
Unisys Corporation - Blue Bell PA
International Classification:
G06F 9/455
Abstract:
Systems and methods for executing non-native instructions in a computing system having a processor configured to execute native instructions are provided. A dynamic translator uses instruction code translation in parallel with just-in-time (JIT) compilation to execute the non-native instructions. Non-native instructions may be interpreted to generate instruction codes, which may be stored in a shadow memory. During a subsequent scheduling of a non-native instruction for execution, the corresponding instruction code may be retrieved from the shadow memory and executed, thereby avoiding reinterpreting the non-native instruction. In addition, the JIT compiler may compile instruction codes to generate native instructions, which may be made available for execution, further speeding up the execution process. A system implementing the aforementioned translator may improve performance and speed associated with executing non-native instructions by optimizing the use of instruction codes and JIT-compiled native instructions corresponding to the instruction codes when executing the non-native instructions.

Updating Compiled Native Instruction Paths

US Patent:
2015018, Jul 2, 2015
Filed:
Dec 30, 2013
Appl. No.:
14/143315
Inventors:
Andrew T. Jennings - Minnetonka MN, US
Charles R. Caldarale - Roseville MN, US
Maurice Marks - Roseville MN, US
Kevin Harris - Nashua NH, US
Assignee:
Unisys Corporation - Blue Bell PA
International Classification:
G06F 9/455
Abstract:
Systems and methods for executing non-native instructions in a computing system having a processor configured to execute native instructions are provided. A dynamic translator uses instruction code translation in parallel with just-in-time (JIT) compilation to execute the non-native instructions. Non-native instructions may be interpreted to generate instruction codes, which may be stored in a shadow memory. During a subsequent scheduling of a non-native instruction for execution, the corresponding instruction code may be retrieved from the shadow memory and executed, thereby avoiding reinterpreting the non-native instruction. In addition, the JIT compiler may compile instruction codes to generate native instructions, which may be made available for execution, further speeding up the execution process. A system implementing the aforementioned translator may improve performance and speed associated with executing non-native instructions by optimizing the use of instruction codes and JIT-compiled native instructions corresponding to the instruction codes when executing the non-native instructions.

Dedicating Processing Resources To Just-In-Time Compilers And Instruction Processors In A Dynamic Translator

US Patent:
2015018, Jul 2, 2015
Filed:
Dec 30, 2013
Appl. No.:
14/143308
Inventors:
Andrew T. Jennings - Minnetonka MN, US
Charles R. Caldarale - Roseville MN, US
Gregory Heimann - Roseville MN, US
Maurice Marks - Roseville MN, US
Kevin Harris - Nashua NH, US
Assignee:
Unisys Corporation - Blue Bell PA
International Classification:
G06F 9/455
Abstract:
Systems and methods for executing non-native instructions in a computing system having a processor configured to execute native instructions are provided. A dynamic translator uses instruction code translation in parallel with just-in-time (JIT) compilation to execute the non-native instructions. Non-native instructions may be interpreted to generate instruction codes, which may be stored in a shadow memory. During a subsequent scheduling of a non-native instruction for execution, the corresponding instruction code may be retrieved from the shadow memory and executed, thereby avoiding reinterpreting the non-native instruction. In addition, the JIT compiler may compile instruction codes to generate native instructions, which may be made available for execution, further speeding up the execution process. A system implementing the aforementioned translator may improve performance and speed associated with executing non-native instructions by optimizing the use of instruction codes and JIT-compiled native instructions corresponding to the instruction codes when executing the non-native instructions.

Defining An Instruction Path To Be Compiled By A Just-In-Time (Jit) Compiler

US Patent:
2015018, Jul 2, 2015
Filed:
Dec 30, 2013
Appl. No.:
14/143341
Inventors:
Andrew T. Jennings - Minnetonka MN, US
Charles R. Caldarale - Roseville MN, US
Maurice Marks - Roseville MN, US
Kevin Harris - Nashua NH, US
Assignee:
Unisys Corporation - Blue Bell PA
International Classification:
G06F 9/455
Abstract:
Systems and methods for executing non-native instructions in a computing system having a processor configured to execute native instructions are provided. A dynamic translator uses instruction code translation in parallel with just-in-time (JIT) compilation to execute the non-native instructions. Non-native instructions may be interpreted to generate instruction codes, which may be stored in a shadow memory. During a subsequent scheduling of a non-native instruction for execution, the corresponding instruction code may be retrieved from the shadow memory and executed, thereby avoiding reinterpreting the non-native instruction. In addition, the JIT compiler may compile instruction codes to generate native instructions, which may be made available for execution, further speeding up the execution process. A system implementing the aforementioned translator may improve performance and speed associated with executing non-native instructions by optimizing the use of instruction codes and JIT-compiled native instructions corresponding to the instruction codes when executing the non-native instructions.

Isbn (Books And Publications)

Macroeconomics In Focus

Author:
Andrew Jennings
ISBN #:
0070848882

The Great Olympic Swindle: When The World Wanted Its Games Back

Author:
Andrew Jennings
ISBN #:
0743202937

The Lords Of The Rings: Power, Money, And Drugs In The Modern Olympics

Author:
Andrew Jennings
ISBN #:
0773726365

Possible Relatives

David Jennings  Dawn M Jennings  Deanna K Jennings  Deborah L Jennings  Dana L Jennings  Aaron G Jennings  Dee S Jennings  Andrew C Johnston  Andrew D Stanek  Andrew J Stanfill 

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