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Anil K Aggarwal, Age 6012665 NW Majestic Sequoia Way, Portland, OR 97229

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Known as:
Anil Te Aggarwal Anil C Aggarwal Anil M Aggarwal Anisha Aggarwal Anil K Trs Arun Aggarwal Ashish Aggarwal Anil Aggarwar Aggarwal K Anil

Anil Aggarwal Phones & Addresses

12665 NW Majestic Sequoia Way, Portland, OR 97229 (503) 333-4437

1587 Caitlin Ter, Portland, OR 97229 (503) 644-9511

San Jose, CA

Redmond, WA

Sunderland, MA

Hillsboro, OR

12665 NW Majestic Sequoia Way, Portland, OR 97229 (503) 644-9511

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Work

Position: Food Preparation and Serving Related Occupations

Education

Degree: Bachelor's degree or higher

Mentions for Anil K Aggarwal

Career records & work history

Lawyers & Attorneys

Anil Aggarwal Photo 1

Anil Aggarwal - Lawyer

Office:
Fasken Martineau DuMoulin LLP
Specialties:
Corporate / Commercial, Securities and Mergers & Acquisitions, Investment Products & Wealth Management
ISLN:
913053339
Admitted:
1998
University:
University of Toronto, 1991; University of Toronto, 1991; University of Toronto, 1994; University of Toronto, 1994
Law School:
Queen's University, LL.B., 1996

Medicine Doctors

Anil Aggarwal Photo 2

Anil Aggarwal

Specialties:
Internal Medicine
Education:
Wayne State University (1986)
Anil Aggarwal Photo 3

Anil Kumar Aggarwal

Specialties:
Anesthesiology
Internal Medicine
Education:
Wayne State University (1986) Internal Medicine

License Records

Anil Aggarwal

Licenses:
License #: 336042737 - Expired
Issued Date: Apr 13, 1990
Expiration Date: Jul 31, 1993
Type: Licensed Physician Controlled Substance(Schedules Ii Iii Iv V )
License #: 036079745 - Expired
Issued Date: Mar 2, 1990
Expiration Date: Jul 31, 1993
Type: Licensed Physician And Surgeon

Anil Aggarwal resumes & CV records

Resumes

Anil Aggarwal Photo 40

Owner At Aggarwal Insurance Agency

Position:
Insurance at Anil Aggarwal Insurance Agency, Owner at Aggarwal Insurance Agency
Location:
Ventura, California
Industry:
Insurance
Work:
Anil Aggarwal Insurance Agency since Mar 2008
Insurance Aggarwal Insurance Agency since Mar 2008
Owner Saint Bonaventure High School Sep 2009 - Jun 2012
Booster Club President Pump It Up of Ventura Oct 2003 - Jan 2008
Owner/President
Education:
Delhi University
BA, History Ventura County Entrepreneur Academy
Graduate, Business Management
Skills:
Auto Insurance, Home, Life Insurance, Boat, Motorcycle, RV & Trailers, Business Insurance, General Liability, Workers Compensation, Surety Bonds, Professional Liability, Health Insurance, Long Term Care Insurance, Disability Insurance, International Travel & Health Insurance, Long-term Care, Small Business, Insurance, General Insurance, Fixed Annuities, Commercial Insurance, Term Life Insurance, Employee Benefits, Underwriting, Property & Casualty Insurance, Legal Liability, Umbrella Insurance
Interests:
Camping, Traveling, Community Volunteering
Honor & Awards:
Multiple sales and production awards from Farmers Insurance Family of Companies - Blue Vase - Toppers Club - Century Award - Gold Level
Languages:
English
Hindi
Anil Aggarwal Photo 41

Senior Principal Engineer

Location:
Portland, OR
Industry:
Computer Software
Work:
Intel Corporation
Senior Principal Engineer
Anil Aggarwal Photo 42

Anil Aggarwal

Skills:
Microsoft Office

Publications & IP owners

Us Patents

Queued Locks Using Monitor-Memory Wait

US Patent:
7213093, May 1, 2007
Filed:
Jun 27, 2003
Appl. No.:
10/608708
Inventors:
Per Hammarlund - Hillsboro OR, US
James B. Crossland - Banks OR, US
Anil Aggarwal - Portland OR, US
Shivnandan D. Kaushik - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 12/14
G06F 9/46
G06F 13/00
US Classification:
710200, 718102, 718104, 719315
Abstract:
A method, apparatus, and system are provided for monitoring locks using monitor-memory wait. According to one embodiment, a node associated with a contended lock is monitored; and a processor seeking the contended lock is put to sleep until a monitor event occurs.

Queued Locks Using Monitor-Memory Wait

US Patent:
7328293, Feb 5, 2008
Filed:
Mar 9, 2007
Appl. No.:
11/716377
Inventors:
Per Hammarlund - Hillsboro OR, US
James B. Crossland - Banks OR, US
Anil Aggarwal - Portland OR, US
Shivnandan D. Kaushik - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 12/00
G06F 9/46
G06F 9/50
US Classification:
710200, 718102, 718104, 719315
Abstract:
A method, apparatus, and system are provided for monitoring locks using monitor-memory wait. According to one embodiment, a node associated with a contended lock is monitored; and a processor seeking the contended lock is put to sleep until a monitor event occurs.

Queued Locks Using Monitor-Memory Wait

US Patent:
7640384, Dec 29, 2009
Filed:
Sep 20, 2007
Appl. No.:
11/903249
Inventors:
Per Hammarlund - Hillsboro OR, US
James B. Crossland - Banks OR, US
Anil Aggarwal - Portland OR, US
Shivnandan D. Kaushik - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 12/00
G06F 9/46
G06F 13/00
US Classification:
710200, 718102, 718104, 719315
Abstract:
A method, apparatus, and system are provided for monitoring locks using monitor-memory wait. In one embodiment, a memory to store instructions to perform functions of a monitoring mechanism is provided. The monitoring mechanism having a first logic to cause a processor to exit a sleep state in response to an event, wherein exiting the sleep state comprises resuming control of processing resources that were relinquished by the processor during the sleep state. The monitoring mechanism having a second logic to disable monitoring of a node associated with a contended lock after the processor exits the sleep state.

Mechanism To Emulate User-Level Multithreading On An Os-Sequestered Sequencer

US Patent:
7810083, Oct 5, 2010
Filed:
Dec 30, 2004
Appl. No.:
11/026597
Inventors:
Gautham N. Chinya - Hillsboro OR, US
Hong Wang - Santa Clara CA, US
Xiang Zou - Beaverton OR, US
James Paul Held - Portland OR, US
Prashant Sethi - Folsom CA, US
Trung Diep - San Jose CA, US
Anil Aggarwal - Portland OR, US
Baiju V. Patel - Portland OR, US
Shiv Kaushik - Portland OR, US
Bryant Bigbee - Scottsdale AZ, US
John Shen - San Jose CA, US
Richard A. Hankins - San Jose CA, US
John L. Reid - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 9/45
G06F 9/40
G06F 7/38
G06F 9/46
US Classification:
717149, 717134, 717151, 712203, 712235, 718100, 718107, 718108
Abstract:
Method, apparatus and system embodiments to provide user-level creation, control and synchronization of OS-invisible “shreds” of execution via an abstraction layer for a system that includes one or more sequencers that are sequestered from operating system control. For at least one embodiment, the abstraction layer provides sequestration logic, proxy execution logic, transition detection and shred suspension logic, and sequencer arithmetic logic. Other embodiments are also described and claimed.

Method And Apparatus Of Power Management Of Processor

US Patent:
7818596, Oct 19, 2010
Filed:
Dec 14, 2006
Appl. No.:
11/638700
Inventors:
Russell J. Fenger - Beaverton OR, US
Anil Aggarwal - Portland OR, US
Efraim Rotem - Haifa, IL
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1/00
US Classification:
713322, 713300, 713320, 713502
Abstract:
Briefly, a processor and a method of setting a performance state of a turbo mode enabled processor. The method includes determining an effective performance state over a predetermined time period, calculating a target performance state based on core utilization and the effective performance state over the predetermined time period and setting the turbo mode enabled processor to a turbo mode performance state.

Programmable Event Driven Yield Mechanism Which May Activate Service Threads

US Patent:
7849465, Dec 7, 2010
Filed:
May 19, 2005
Appl. No.:
11/134687
Inventors:
Xiang Zou - Portland OR, US
Hong Wang - Fremont CA, US
Scott Dion Rodgers - Hillsboro OR, US
Darrell D. Boggs - Aloha OR, US
Bryant Bigbee - Scottsdale AZ, US
Shivanandan Kaushik - Portland OR, US
Anil Aggarwal - Portland OR, US
Ittai Anati - Haifa, IL
Doron Orenstein - Haifa, IL
Per Hammarlund - Hillsboro OR, US
John Shen - San Jose CA, US
Larry O. Smith - Beaverton OR, US
James B. Crossland - Banks OR, US
Chris J. Newburn - South Beloit IL, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 9/46
G06F 13/24
G06F 7/38
US Classification:
718104, 710260, 712244
Abstract:
Method, apparatus, and system for a programmable event driven yield mechanism that may activate other threads. The yield mechanism may allow triggering of a service thread that may execute currently with a main thread upon occurrence of an architecturally-defined condition. The service thread may be activated, in response to the condition, with limited intervention of an operating system. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect an architecturally-defined condition. The apparatus may include an event handler to handle a yield event generated when the architecturally-defined condition has been detected. An architectural mechanism, including processor instructions and channel registers, may be utilized to allow user-level code to enable the yield event mechanism. Other embodiments are also described and claimed.

System And Method For Selecting Optimal Processor Performance Levels By Using Processor Hardware Feedback Mechanisms

US Patent:
7917789, Mar 29, 2011
Filed:
Sep 28, 2007
Appl. No.:
11/864800
Inventors:
Russell J. Fenger - Beaverton OR, US
Anil Aggarwal - Portland OR, US
Shiv Kaushik - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1/08
US Classification:
713322, 713300, 713310, 713323
Abstract:
An embodiment of the present invention is a system and method relating to adaptive power management using hardware feedback to select optimal processor frequencies and reduce power/watt. In at least one embodiment, the present invention is intended to optimize processor frequency and power/watt usage based on the hardware feedback and processor stall behavior.

Method, System, And Apparatus For Rerouting Interrupts In A Multi-Core Processor

US Patent:
7962771, Jun 14, 2011
Filed:
Dec 31, 2007
Appl. No.:
11/967799
Inventors:
Justin Song - Olympia WA, US
Devadatta V. Bodas - Federal Way WA, US
Ohad Falik - Kfar-Saba, IL
Alon Naveh - Ramat Hasharon, IL
Ilan Pardo - Ramat Hasharon, IL
Anil Aggarwal - Portland OR, US
Sridhar Muthrasanallur - Puyallup WA, US
James B. Crossland - Banks OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1/00
US Classification:
713300, 713324
Abstract:
A method, system, and apparatus may route an interrupt to a first core of a plurality of cores of a multi-core system. If the first core is in an idle or low power state, or operating in a power state at or below a threshold power state, a core in a least idle state may be found. The interrupt may be rerouted to and processed by the core in the least idle state. Cores in a multi-core system may be rated based on for example, power states or other characteristics, and interrupts may be assigned based on these ratings. Other embodiments are described and claimed.

Possible Relatives

Gopal M Aggarwal  Krishan K Aggarwal  Manju Aggarwal  Monica Aggarwal  Nidhi I Aggarwal  Pooja Aggarwal  Prerna Aggarwal  Anil B Khan  Anil M Kumar  Anil A Pal 

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