Anthony Clayton Krauth, Age 5710204 Edna St, Boise, ID 83704

6835503, Dec 28, 2004

Apr 12, 2002

10/122031

Anthony C. Krauth - Boise ID

Micron Technology, Inc. - Boise ID

G03F 900

430 5, 359838, 427162, 428143

The present invention relates to fabricating a reticle or mask for use in an extreme ultraviolet (âEUVâ) photolithographic process. The EUV reticle comprises a substrate, a planarizing layer formed over a surface of the substrate, and a reflective layer deposited in contact with the planarizing layer. The planarizing layer comprises a material that has superior surface flatness properties and provides a flat surface upon which the reflective layer is deposited. The planarizing layer is spin-coated onto the substrate and comprises a material such as an anti-reflective material, a dielectric material, or a polymer. Since the reflective layer is deposited over the flat surface provided by the planarizing layer, the reflective layer is not compromised by defects in the surface of the substrate.

7387853, Jun 17, 2008

Dec 3, 2004

11/003806

Anthony C. Krauth - Boise ID, US

Micron Technology, Inc. - Boise ID

G03F 1/00

430 5

The present invention relates to fabricating a reticle or mask for use in an extreme ultraviolet (“EUV”) photolithographic process. The EUV reticle comprises a substrate, a planarizing layer formed over a surface of the substrate, and a reflective layer deposited in contact with the planarizing layer. The planarizing layer comprises a material that has superior surface flatness properties and provides a flat surface upon which the reflective layer is deposited. The planarizing layer is spin-coated onto the substrate and comprises a material such as an anti-reflective material, a dielectric material, or a polymer. Since the reflective layer is deposited over the flat surface provided by the planarizing layer, the reflective layer is not compromised by defects in the surface of the substrate.

7972926, Jul 5, 2011

Jul 2, 2009

12/497128

David A. Kewley - Boise ID, US
Brian Cleereman - Boise ID, US
Stephen W. Russell - Boise ID, US
Rex Stone - Albuquerque NM, US
Anthony C. Krauth - Boise ID, US

Micron Technology, Inc. - Boise ID

H01L 21/336

438264, 430313, 257E21038

Some embodiments include methods of forming memory. A series of photoresist features may be formed over a gate stack, and a placeholder may be formed at an end of said series. The placeholder may be spaced from the end of said series by a gap. A layer may be formed over and between the photoresist features, over the placeholder, and within said gap. The layer may be anisotropically etched into a plurality of first vertical structures along edges of the photoresist features, and into a second vertical structure along an edge of the placeholder. A mask may be formed over the second vertical structure. Subsequently, the first vertical structures may be used to pattern string gates while the mask is used to pattern a select gate. Some embodiments include methods of forming conductive runners, and some embodiments may include semiconductor constructions.

8609489, Dec 17, 2013

Jun 6, 2011

13/154259

David A. Kewley - Boise ID, US
Brian Cleereman - Boise ID, US
Stephen W. Russell - Boise ID, US
Rex Stone - Albuquerque NM, US
Anthony C. Krauth - Boise ID, US

Micron Technology, Inc. - Boise ID

H01L 21/336

438264, 438313, 257E21038, 257E21023, 257E21024, 257206, 257E21027

Some embodiments include methods of forming memory. A series of photoresist features may be formed over a gate stack, and a placeholder may be formed at an end of said series. The placeholder may be spaced from the end of said series by a gap. A layer may be formed over and between the photoresist features, over the placeholder, and within said gap. The layer may be anisotropically etched into a plurality of first vertical structures along edges of the photoresist features, and into a second vertical structure along an edge of the placeholder. A mask may be formed over the second vertical structure. Subsequently, the first vertical structures may be used to pattern string gates while the mask is used to pattern a select gate. Some embodiments include methods of forming conductive runners, and some embodiments may include semiconductor constructions.

6207357, Mar 27, 2001

Apr 23, 1999

9/299221

Anthony C. Krauth - Boise ID

Micron Technology, Inc. - Boise ID

G03C5/00

430327

Methods of forming layers of photoresist and apparatus for forming photoresist are described. In one embodiment, a wafer is provided and photoresist is applied thereover. The wafer is rotated while the photoresist is baked. In another embodiment, a wafer having photoresist formed thereover is positioned at a baking station. After positioning, the wafer is moved while exposed to baking conditions at the station. In another embodiment, a wafer having photoresist applied thereover is positioned on a rotatable hot plate at a photoresist baking station. The rotatable hot plate is rotated during at least some of the time the wafer is baked at the station. In another embodiment, photoresist is applied over a wafer surface and into a predefined non-uniform thickness over the surface. The non-uniform thickness is modified over the surface into a more uniform thickness while the photoresist is baked.

2014008, Mar 27, 2014

Dec 4, 2013

14/097003

- Boise ID, US
Brian Cleereman - Boise ID, US
Stephen W. Russell - Boise ID, US
Rex Stone - Albuquerque NM, US
Anthony C. Krauth - Boise ID, US

Micron Technology, Inc. - Boise ID

H01L 21/3213
H01L 21/28

438669

Some embodiments include methods of forming memory. A series of photoresist features may be formed over a gate stack, and a placeholder may be formed at an end of said series. The placeholder may be spaced from the end of said series by a gap. A layer may be formed over and between the photoresist features, over the placeholder, and within said gap. The layer may be anisotropically etched into a plurality of first vertical structures along edges of the photoresist features, and into a second vertical structure along an edge of the placeholder. A mask may be formed over the second vertical structure. Subsequently, the first vertical structures may be used to pattern string gates while the mask is used to pattern a select gate. Some embodiments include methods of forming conductive runners, and some embodiments may include semiconductor constructions.