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Bayard K Johnson, Age 59107 Baker Dr, Clairton, PA 15025

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Known as:
Bayard Karen Johnson Bayard Johnson Johnson
Related to:
David L Kelly 58

Bayard Johnson Phones & Addresses

Clairton, PA

Lake Saint Louis, MO

1020 Chatham Park Dr APT K, Pittsburgh, PA 15216

Allegheny, PA

Jefferson Hls, PA

Lake Saint Louis, MO

Work

Company: Taft Stettinius & Hollister LLP Address:

Mentions for Bayard K Johnson

Career records & work history

Lawyers & Attorneys

Bayard Johnson Photo 1

Bayard Johnson - Lawyer

Office:
Taft Stettinius & Hollister LLP
Specialties:
Business & Finance, Mergers & Acquisitions, Lending & Corporate Finance, Private Equity, Venture Capital and Emerging Companies, Technology, International Law, Communications / Media
ISLN:
921066154
Admitted:
2009
University:
University of California at San Diego, B.A., 2002
Law School:
Washington University School of Law in St. Louis, J.D., 2009

Bayard Johnson resumes & CV records

Resumes

Bayard Johnson Photo 20

Administrative Assistant At German-American Heritage Foundation Of The Usa

Bayard Johnson Photo 21

Senior Scientist, Solar Materials

Location:
107 Baker Dr, Clairton, PA 15025
Industry:
Semiconductors
Work:
Sunedison
Senior Scientist, Solar Materials Gt Advanced Technologies Jan 2009 - Aug 2014
Senior Scientist, Manager Numerical Modeling, Manager Ccz Process Development Bettis Atomic Power Laboratory Jan 2000 - Jan 2009
Senior Scientist Memc Electronic Materials May 1996 - Jan 2000
Research Scientist Chatham College Jan 1995 - Jun 1996
Adjunct Professor
Education:
Carnegie Mellon University 1989 - 1995
Doctorates, Doctor of Philosophy, Physics Trinity College - Hartford 1984 - 1988
Bachelors, Bachelor of Science, Physics
Skills:
Materials Science, Physics, Silicon, R&D, Semiconductors, Simulations, Photovoltaics, Process Simulation, Materials, Electronics, Numerical Analysis, Fluid Dynamics, Project Management, Thermodynamics, Heat Transfer, Sensors, Corrosion, 5S, Abaqus, Numerical Modeling, Process Development, Phase Transformations, Goal Setting, Technology Transfer, Silicon Crystal Growth, Zircaloy, Fortran, Visual Basic, Fluent, Cgsim

Publications & IP owners

Us Patents

Low Defect Density Epitaxial Wafer And A Process For The Preparation Thereof

US Patent:
6632278, Oct 14, 2003
Filed:
Apr 30, 2002
Appl. No.:
10/135597
Inventors:
Robert A. Falster - London, GB
Joseph C. Holzer - St. Charles MO
Steve A. Markgraf - Chandler AZ
Paolo Mutti - Milan, IT
Seamus A. McQuaid - Victoria, ES
Bayard K. Johnson - Jefferson Hills PA
Assignee:
MEMC Electronic Materials, Inc. - St. Peters MO
International Classification:
C30B 2906
US Classification:
117 84, 117 13, 117 15, 117 20, 117 28, 428 641, 428248, 428446
Abstract:
The present invention relates to an epitaxial wafer comprising single crystal silicon substrate and an epitaxial layer deposited thereon. The substrate comprises an axially symmetric region which is free of agglomerated intrinsic point defects and wherein silicon self-interstitials are the predominant intrinsic point defect in the axially symmetric region. The present invention further relates to a process for producing such an epitaxial wafer.

Vacancy, Dominsated, Defect-Free Silicon

US Patent:
6840997, Jan 11, 2005
Filed:
Oct 24, 2001
Appl. No.:
10/000545
Inventors:
Robert A. Falster - London, GB
Joseph C. Holzer - St. Charles MO, US
Steve A. Markgraf - Plymouth MN, US
Paolo Mutti - Milan, IT
Seamus A. McQuaid - Vitoria, ES
Bayard K. Johnson - Jefferson Hills PA, US
Assignee:
MEMC Electronic Materials, Inc. - St. Peters MO
International Classification:
C30B 3100
US Classification:
117 3
Abstract:
The present invention relates to a process for growing a single crystal silicon. The process including controlling a growth velocity, v, and an average axial temperature gradient, G, during the growth of the constant diameter portion of the crystal over the temperature range from solidification to a temperature of no less than about 1325 C. , to cause the formation of a first axially symmetrical region in which vacancies, upon cooling of the ingot from the solidification temperature, are the predominant intrinsic point defect and which is substantially free of agglomerated intrinsic point defects, wherein the first axially symmetric region has a width of at least about 50% of the radius of the constant diameter portion of the ingot.

Low Defect Density, Ideal Oxygen Precipitating Silicon

US Patent:
7229693, Jun 12, 2007
Filed:
Feb 16, 2005
Appl. No.:
11/058996
Inventors:
Robert J. Falster - London, GB
Joseph C. Holzer - St. Charles MO, US
Marco Cornara - Galliate, IT
Daniela Gambaro - Galliate, IT
Massimiliano Olmo - Novara, IT
Steve A. Markgraf - Maple Grove MN, US
Paolo Mutti - Milan, IT
Seamus A. McQuaid - Vitoria, ES
Bayard K. Johnson - Jefferson Hills PA, US
Assignee:
MEMC Electronic Materials, Inc. - St. Peters MO
International Classification:
B32B 9/04
US Classification:
428446, 428 641, 117932
Abstract:
The present invention is directed to a silicon wafer which, during the heat treatment cycles of essentially any arbitrary electronic device manufacturing process, may form an ideal, non-uniform depth distribution of oxygen precipitates and may additionally contain an axially symmetric region which is substantially free of agglomerated intrinsic point defects.

Process For Forming Low Defect Density, Ideal Oxygen Precipitating Silicon

US Patent:
7442253, Oct 28, 2008
Filed:
May 24, 2007
Appl. No.:
11/753294
Inventors:
Robert J. Falster - London, GB
Joseph C. Holzer - St. Charles MO, US
Marco Cornara - Galliate, IT
Daniela Gambaro - Galliate, IT
Massimiliano Olmo - Novara, IT
Steve A. Markgraf - Maple Grove MN, US
Paolo Mutti - Milan, IT
Seamus A. McQuaid - Vitoria, ES
Bayard K. Johnson - Jefferson Hills PA, US
Assignee:
MEMC Electronic Materials, Inc. - St. Peters MO
International Classification:
C30B 25/12
US Classification:
117 89, 117 19, 117 20, 117 84
Abstract:
The present invention is directed to a process for producing a silicon wafer which, during the heat treatment cycles of essentially any arbitrary electronic device manufacturing process, may form an ideal, non-uniform depth distribution of oxygen precipitates and may additionally contain an axially symmetric region which is substantially free of agglomerated intrinsic point defects. The process either comprises exposing the wafer's front and back surfaces to different atmospheres, or thermally annealing two wafers in a face-to-face arrangement.

Vacancy, Dominated, Defect-Free Silicon

US Patent:
2003005, Mar 20, 2003
Filed:
Jul 3, 2002
Appl. No.:
10/189139
Inventors:
Robert Falster - London, GB
Joseph Holzer - St. Charles MO, US
Steve Markgraf - Chandler AZ, US
Paolo Mutti - Milan, IT
Seamus McQuaid - Vitoria, ES
Bayard Johnson - Jefferson Hills PA, US
Assignee:
MEMC Electronic Materials, Inc.
International Classification:
C30B015/00
US Classification:
117/013000, 428/001000
Abstract:
The present invention relates to single crystal silicon, in ingot or wafer form, which contains an axially symmetric region in which vacancies are the predominant intrinsic point defect and which is substantially free of agglomerated vacancy intrinsic point defects, wherein the first axially symmetric region has a width which is at least about 50% of the length of the radius of the ingot, and a process for the preparation thereof.

Process For Suppressing The Nucleation And/Or Growth Of Interstitial Type Defects By Controlling The Cooling Rate Through Nucleation

US Patent:
2003019, Oct 23, 2003
Filed:
May 6, 2003
Appl. No.:
10/430483
Inventors:
Kirk McCallum - Warrenton MO, US
W. Alexander - Valrico FL, US
Mohsen Banan - Grove MO, US
Robert Falster - London, GB
Joseph Holzer - St. Charles MO, US
Bayard Johnson - Jefferson Hills PA, US
Chang Kim - St. Louis MO, US
Steven Kimbel - St. Charles MO, US
Zheng Lu - St. Charles MO, US
Paolo Mutti - Merano, IT
Vladimir Voronkov - Merano, IT
Jeffrey Libbert - O'Fallon MO, US
Assignee:
MEMC Electronic Materials, Inc.
International Classification:
C30B015/00
C30B021/06
C30B027/02
C30B028/10
C30B030/04
US Classification:
117/013000
Abstract:
The present invention relates to a process for growing a single crystal silicon ingot, which contains an axially symmetric region having a predominant intrinsic point defect and which is substantially free of agglomerated intrinsic point defects in that region. The process comprising cooling the ingot from the temperature of solidification to a temperature of less than 800 C. and, as part of said cooling step, quench cooling a region of the constant diameter portion of the ingot having a predominant intrinsic point defect through the temperature of nucleation for the agglomerated intrinsic point defects for the intrinsic point defects which predominate in the region.

Process For Producing Low Defect Density Silicon

US Patent:
2004008, May 13, 2004
Filed:
Oct 14, 2003
Appl. No.:
10/685251
Inventors:
Robert Falster - London, GB
Joseph Holzer - St. Charles MO, US
Steve Markgraf - Plymouth MN, US
Paolo Mutti - Milan, IT
Seamus McQuaid - Victoria, ES
Bayard Johnson - Jefferson Hills PA, US
Assignee:
MEMC Electronic Materials, Inc.
International Classification:
C30B015/00
C30B021/06
C30B027/02
C30B028/10
C30B030/04
US Classification:
117/013000
Abstract:
The present invention relates to single crystal silicon, in ingot or wafer form, which contains an axially symmetric region which is free of agglomerated intrinsic point defects, and a process for the preparation thereof.

Vacancy-Dominated, Defect-Free Silicon

US Patent:
2005023, Oct 27, 2005
Filed:
Apr 8, 2005
Appl. No.:
11/102241
Inventors:
Robert Falster - London, GB
Joseph Holzer - St. Charles MO, US
Steve Markgraf - Maple Grove MN, US
Paolo Mutti - Milan, IT
Seamus McQuaid - Vitoria, ES
Bayard Johnson - Jefferson Hills PA, US
Assignee:
MEMC Electronic Materials, Inc. - St. Peters MO
International Classification:
H01L029/12
US Classification:
428620000
Abstract:
The present invention relates to single crystal silicon, in ingot or wafer form, having an axially symmetric vacancy dominated region and an axially symmetric silicon self-interstitial dominated region. Both the vacancy dominated and the silicon self-interstitial dominated regions are substantially free of agglomerated intrinsic point defects. The vacancy dominated region has a radial width of at least 15 mm and/or includes the central axis and the silicon self-interstitial dominated region is annular in shape and extends radially outward from the vacancy dominated region to the peripheral edge of the ingot or wafer. In ingot form, the axially symmetric regions have an axial length which is at least 20% of the length of the constant diameter portion of the ingot.

Isbn (Books And Publications)

Damned Right

Author:
Bayard Johnson
ISBN #:
0932511848

Possible Relatives

D Johnson  Dawna M Johnson  Dayle D Johnson  Daymon A Johnson  Dayna M Johnson  Dayne E Johnson  Daysha D Johnson  Bayard L Pickett  Bayard D Clarkson 

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