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Benson K Chau, Age 41San Jose, CA

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Known as:
Chau Benson Ben Chau Kinh Benson
Related to:
Nhu T Chau 46

Benson Chau Phones & Addresses

San Jose, CA

Los Angeles, CA

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Resumes

Benson Chau Photo 15

Associate Level 4

Location:
San Gabriel, CA
Work:
In and Out Burger
Associate Level 4
Benson Chau Photo 16

Benson Chau

Location:
Los Angeles, CA

Publications & IP owners

Us Patents

Intelligent Detection Interface For Wireless Devices

US Patent:
2013018, Jul 18, 2013
Filed:
Jan 17, 2013
Appl. No.:
13/744374
Inventors:
MARVELL WORLD TRADE LTD. - ST. MICHAEL, BB
Benson Chau - Santa Clara CA, US
Venkatachalam Shanmugasundaram - Cupertino CA, US
Ken Yeung - Cupertino CA, US
Assignee:
MARVELL WORLD TRADE LTD. - ST. MICHAEL
International Classification:
H04W 52/02
US Classification:
455418
Abstract:
In a method for controlling a wireless device assembly coupled to a host assembly, a clock signal is received at the wireless device assembly from the host assembly. The clock signal is supplied to an interface module in the wireless device assembly during a power save mode of the wireless device assembly and is used to operate the interface module. An initialization command is received at the wireless device assembly from the host assembly and is detected with the interface module. In response to detecting the initialization command, at least a portion of the wireless device assembly, other than the interface module, is activated.

Clock And Phase Alignment Between Physical Layers And Controller

US Patent:
2023005, Feb 23, 2023
Filed:
Aug 18, 2021
Appl. No.:
17/405854
Inventors:
- San Jose CA, US
Benson CHAU - Sunnyvale CA, US
Tomai KNOPP - San Jose CA, US
International Classification:
H03K 5/02
H03K 23/60
H03K 19/173
H03K 19/20
Abstract:
An integrated circuit (IC) for clock and phase aligning and synchronization between physical (PHY) layers and a communications controller is provided. The IC includes a clock multiplier configured to multiply a frequency of the clock signal from a plurality of PHY layers to match a frequency of a clock signal of the controller, wherein the clock signal from the plurality of PHY layers is less than the frequency of the clock signal of the controller. IC support circuitry is configured to provide the multiplied clock signal to the controller. The IC includes a first clock divider configured to divide the frequency of the multiplied clock signal and to output the divided clock signal to the controller. The IC includes a phase alignment circuit configured to align phases of one or more data signals based on a phase of the clock signal and a phase of the multiplied clock signal.

Possible Relatives

Cynthia V Chau  Dat T Chau  Diana P Chau  Diane M Chau  Diem H Chau  Dieu V Chau  Duong M Chau  Benson H Mcgrath  Benson J Lamp  Benson L Ledbetter 

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