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Bharath C Iyer, Age 48401 Little Texas Ln, Austin, TX 78745

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Known as:
Bharath C Lyer Bharath Dyer Iyer Bharath
Related to:
Sivaram Chandran Iyer

Bharath Iyer Phones & Addresses

401 Little Texas Ln, Austin, TX 78745

Kyle, TX

4320 Rowalt Dr, College Park, MD 20740 (301) 779-8473

4601 West Hwy, Riverdale, MD 20737 (301) 779-8473

Castro Valley, CA

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Bharath Iyer resumes & CV records

Resumes

Bharath Iyer Photo 24

Microprocessor Design Engineer At Sarc

Position:
Staff Design Engineer at Samsung Austin R&D Center
Location:
Austin, Texas Area
Industry:
Semiconductors
Work:
Samsung Austin R&D Center - Austin, Texas since Dec 2012
Staff Design Engineer AMD - Austin, Texas Jan 2004 - Dec 2012
Member of Technical Staff System & Computer Architecture Lab, Univ of Maryland - College Park, Maryland Jan 2002 - Dec 2003
Research Assistant Motorola India Electronics Ltd. - Bangalore, India Aug 1999 - Aug 2000
DSP Software Engineer Communications & DSP Lab, IIT-Delhi - New Delhi Area, India Aug 1997 - Jul 1999
Research Associate
Education:
University of Maryland College Park 2000 - 2003
MS, Computer Engg. Indian Institute of Technology, Delhi 1997 - 1999
MS (Research), Wireless Comm & Signal Processing University of Mumbai 1993 - 1997
B.E., Electronics & Telecommunications
Skills:
Computer Architecture, RTL design, Microcode, Logic Design, Verilog, Assembly Language, Cache Coherency, Virtualization, DSP, Power Management, SystemVerilog, Performance Analysis, Microprocessors, Embedded Systems, Functional Verification, Debugging, Processors, Semiconductors, X86, Power Analysis, Microarchitecture, SoC, C++, C, CPU design, X86 Virtualization, Hardware Design, X86_64, Object Oriented Design, Consistency, Digital Signal Processors, Hardware Architecture
Bharath Iyer Photo 25

Senior Engineering Manager

Location:
Austin, TX
Industry:
Semiconductors
Work:
Amd
Senior Engineering Manager Harc Mar 2017 - Jan 2019
Principal Engineer Samsung Electronics Dec 2012 - Mar 2017
Cpu Microarchitect Amd Jan 2004 - Dec 2012
Microcode and Rtl and Dv Roles Motorola Aug 1999 - Aug 2000
Dsp Software Engineer Wesee Iit-Delhi Project Aug 1997 - Jul 1999
Project Associate
Education:
The University of Texas at Austin - Red Mccombs School of Business 2018 - 2019
University of Maryland 2000 - 2003
Master of Science, Masters Indian Institute of Technology, Delhi 1997 - 1999
Master of Science, Masters University of Mumbai 1993 - 1997
Bachelor of Engineering, Bachelors, Telecommunications, Electronics
Skills:
Computer Architecture, Debugging, Microprocessors, Verilog, Rtl Design, Processors, X86, Microarchitecture, C++, C, Soc, Functional Verification, Embedded Systems, Microcode, Digital Signal Processors, Semiconductors, Simulations, Logic Design, Assembly Language, Vlsi, Systemverilog, Performance Analysis, Hardware Architecture, Asic, Cache Coherency, Virtualization, Power Management, Power Analysis, Cpu Design, X86_64, Object Oriented Design, Dsp, X86 Virtualization, Hardware Design, Consistency, Statistical Data Analysis, Machine Learning, Python, Arm Architecture, Predictive Analytics, Predictive Modeling
Languages:
English
Hindi
Spanish
Tamil
Marathi

Possible Relatives

A V Iyer  G Iyer  Kailasam R Iyer  Karthik Iyer  Krishna Iyer  Lakshmi V Iyer  Lalitha M Iyer 

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