Bharath C Iyer, Age 46401 Little Texas Ln, Austin, TX 78745

Bharath Iyer Phones & Addresses

401 Little Texas Ln, Austin, TX 78745

Kyle, TX

College Park, MD

Riverdale, MD

Castro Valley, CA

7626 Crackling Creek Dr, Austin, TX 78736

Work

Position: Clerical/White Collar

Education

Degree: Graduate or professional degree

Mentions for Bharath C Iyer

Resumes and CV

Resumes

Bharath Iyer Photo 1

Senior Engineering Manager

Location:
Austin, TX
Industry:
Semiconductors
Work:
Amd
Senior Engineering Manager
Harc Mar 2017 - Jan 2019
Principal Engineer
Samsung Electronics Dec 2012 - Mar 2017
Cpu Microarchitect
Amd Jan 2004 - Dec 2012
Microcode and Rtl and Dv Roles
Motorola Aug 1999 - Aug 2000
Dsp Software Engineer
Wesee Iit-Delhi Project Aug 1997 - Jul 1999
Project Associate
Education:
The University of Texas at Austin - Red Mccombs School of Business 2018 - 2019
University of Maryland 2000 - 2003
Master of Science, Masters
Indian Institute of Technology, Delhi 1997 - 1999
Master of Science, Masters
University of Mumbai 1993 - 1997
Bachelor of Engineering, Bachelors, Telecommunications, Electronics
Skills:
Computer Architecture, Debugging, Microprocessors, Verilog, Rtl Design, Processors, X86, Microarchitecture, C++, C, Soc, Functional Verification, Embedded Systems, Microcode, Digital Signal Processors, Semiconductors, Simulations, Logic Design, Assembly Language, Vlsi, Systemverilog, Performance Analysis, Hardware Architecture, Asic, Cache Coherency, Virtualization, Power Management, Power Analysis, Cpu Design, X86_64, Object Oriented Design, Dsp, X86 Virtualization, Hardware Design, Consistency, Statistical Data Analysis, Machine Learning, Python, Arm Architecture, Predictive Analytics, Predictive Modeling
Languages:
English
Hindi
Spanish
Tamil
Marathi
Bharath Iyer Photo 2

Microprocessor Design Engineer At Sarc

Position:
Staff Design Engineer at Samsung Austin R&D Center
Location:
Austin, Texas Area
Industry:
Semiconductors
Work:
Samsung Austin R&D Center - Austin, Texas since Dec 2012
Staff Design Engineer
AMD - Austin, Texas Jan 2004 - Dec 2012
Member of Technical Staff
System & Computer Architecture Lab, Univ of Maryland - College Park, Maryland Jan 2002 - Dec 2003
Research Assistant
Motorola India Electronics Ltd. - Bangalore, India Aug 1999 - Aug 2000
DSP Software Engineer
Communications & DSP Lab, IIT-Delhi - New Delhi Area, India Aug 1997 - Jul 1999
Research Associate
Education:
University of Maryland College Park 2000 - 2003
MS, Computer Engg.
Indian Institute of Technology, Delhi 1997 - 1999
MS (Research), Wireless Comm & Signal Processing
University of Mumbai 1993 - 1997
B.E., Electronics & Telecommunications
Skills:
Computer Architecture, RTL design, Microcode, Logic Design, Verilog, Assembly Language, Cache Coherency, Virtualization, DSP, Power Management, SystemVerilog, Performance Analysis, Microprocessors, Embedded Systems, Functional Verification, Debugging, Processors, Semiconductors, X86, Power Analysis, Microarchitecture, SoC, C++, C, CPU design, X86 Virtualization, Hardware Design, X86_64, Object Oriented Design, Consistency, Digital Signal Processors, Hardware Architecture

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