Boris Ostrovsky, Age 56422 Peakham Rd, North Sudbury, MA 01776

Boris Ostrovsky Phones & Addresses

422 Peakham Rd, Sudbury, MA 01776 (978) 764-1252

17 Beechwood Ave, Sudbury, MA 01776

9 Monastery Rd #13, Brighton, MA 02135

1082 Commonwealth Ave, Boston, MA 02215

5 Walbridge St #14, Allston, MA 02134

7 Meridian St, Malden, MA 02148

7 Meridian St #13, Malden, MA 02148

Newton, MA

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Mentions for Boris Ostrovsky

Boris Ostrovsky resumes & CV records

Resumes

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Principal Software Engineer

Location:
Cambridge, MA
Industry:
Information Technology And Services
Work:
Navinet
Principal Software Engineer
Ide 2001 - 2004
Principal Software Engineer
Education:
St. Petersburg Engineering and Economic Institute 1970 - 1975
Skills:
Agile Methodologies, Software Development, Scrum, Object Oriented Design, Sql, C#, Xml, .Net, Web Services, Soap, Design Patterns, Asp.net, Microsoft Sql Server, Javascript, Wcf, Soa, T Sql, Service Oriented Architecture, Database Design, Application Development, Visual Studio, Xslt, Wpf, Tfs, Ajax, Jquery, Windows Communication Foundation, Sql Server, Html, Agile, Ado.net, Oop, Transact Sql, Windows
Boris Ostrovsky Photo 26

Boris Ostrovsky

Publications & IP owners

Wikipedia

Boris Ostrovsky Photo 27

Moscow Rules (Daniel Silva Novel)

Boris Ostrovsky, editor of the independent Moskovsky Gazeta, claims to have exclusive ... Ostrovskys death, accompanied by the recent murders of two other

Us Patents

Method And Device For Dynamic Interrupt Target Selection

US Patent:
7058743, Jun 6, 2006
Filed:
Jul 29, 2002
Appl. No.:
10/207611
Inventors:
Boris Ostrovsky - Sudbury MA, US
Christopher J. Jackson - Westford MA, US
Assignee:
Sun Microsystems, Inc. - Santa Clara CA
International Classification:
G06F 13/24
US Classification:
710260, 718105
Abstract:
A method and device for dynamically targeting interrupts in a computer system. When an operation is initiated, an identifier for the initiator of the operation is stored along with an operation identifier. When an operation completes or needs processor attention due to an error condition or otherwise, the processor or node to interrupt is determined based on the stored indication of the initiator of the operation. An interrupt target data structure may be provided that contains associations between sources that initiate operations and those targets that can service interrupts. If a target scheduled to field an interrupt becomes unavailable, the interrupt can be retargeted to another processor or node by reloading an entry in the interrupt target data structure.

Method And Device For A Context-Based Memory Management System

US Patent:
2003007, Apr 10, 2003
Filed:
Oct 9, 2001
Appl. No.:
09/973279
Inventors:
Boris Ostrovsky - Sudbury MA, US
Daniel Cassiday - Topsfield MA, US
John Feehrer - Westford MA, US
David Wood - Madison WI, US
Pazhani Pillai - Billerica MA, US
Christopher Jackson - Westford MA, US
Mark Hill - Madison WI, US
International Classification:
G06F012/10
US Classification:
711/209000, 711/207000, 711/133000, 711/144000
Abstract:
A method and device for virtual memory support in a computer system using a mapping structure for address translation. Mapping indicators are associated with each process context and each mapping structure entry. When a context is demapped the mapping indicator associated with the context is changed and the mapping indicator in each mapping structure entry is employed to immediately invalidate further memory accesses for that context.

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