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Brett W Murdock, Age 537119 Black Rock Bnd, Round Rock, TX 78681

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Known as:
Brett William Murdock Brett W Mendock
Related to:
Hugh Bush Stewart 77

Brett Murdock Phones & Addresses

7119 Black Rock Bnd, Round Rock, TX 78681 (512) 244-4357

5009 Barlow Dr, Round Rock, TX 78681

Topeka, KS

4701 Staggerbrush Rd, Austin, TX 78749

6600 Elm Creek Cv, Austin, TX 78744 (512) 443-1761

Manhattan, KS

Cedar Rapids, IA

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Work

Company: Musco lighting Jun 2010 Position: Welder

Education

School / High School: University of Iowa- Iowa City, IA 2009 Specialities: Bachelor's

Mentions for Brett W Murdock

Career records & work history

Lawyers & Attorneys

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Brett Murdock - Lawyer

ISLN:
922397432
Admitted:
2012
University:
Chapman Univ SOL, Orange, CA; Univ of California San Diego, La Jolla, CA

Medicine Doctors

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Brett Ross Murdock

Brett Murdock resumes & CV records

Resumes

Brett Murdock Photo 29

Senior Technical Marketing Engineer At Denali Software

Position:
Senior Technical Marketing Engineer at Denali Software
Location:
Austin, Texas Area
Industry:
Semiconductors
Work:
Denali Software since May 2008
Senior Technical Marketing Engineer Sam Bass Fire Department 2002 - 2010
Firefighter / Driver / NREMT-B Freescale Semiconductor Jul 2006 - Apr 2008
Design Manager / Technical Lead Freescale Semiconductor Jan 2006 - Nov 2006
System Architect Motorola Semiconductor Sep 1999 - Dec 2005
Project Leader & IP Creation Team Member Motorola Semiconductor Nov 1997 - Aug 1999
Digital Design Engineer Motorola Semiconductor Feb 1996 - Oct 1997
Freshout :)
Education:
Kansas State University 1989 - 1996
Brett Murdock Photo 30

Product Marketing Manager

Location:
2030 Fortune Dr, San Jose, CA 95131
Industry:
Computer Software
Work:
Synopsys
Product Marketing Manager Synopsys Mar 2016 - Mar 2017
Solutions Architect Uniquify Inc Oct 2014 - Mar 2016
Senior Director, Ip Products Cadence Design Systems Feb 2014 - Sep 2014
Director of Engineering - Ddr Design Ip Customer Support Cadence Design Systems Jun 2010 - Jan 2014
Solutions Architect Denali Software May 2008 - Jun 2010
Senior Technical Marketing Engineer Sam Bass Fire Department 2002 - 2010
Firefighter and Driver and Nremt-B Freescale Semiconductor Jul 2006 - Apr 2008
Design Manager and Technical Lead Freescale Semiconductor Jan 2006 - Nov 2006
System Architect Freescale Semiconductor Sep 1999 - Dec 2005
Project Leader and Ip Creation Team Member Freescale Semiconductor Nov 1997 - Aug 1999
Digital Design Engineer Freescale Semiconductor Feb 1996 - Oct 1997
Freshout
Education:
Kansas State University 1989 - 1996
Bachelors, Bachelor of Science, Electrical Engineering, Computer Engineering
Skills:
Verilog, Soc, Asic, Arm, Semiconductors, Processors, Logic Design, Functional Verification, Tcl, Amba Ahb, Ic, Integrated Circuit Design, Microprocessors, Hardware Architecture, Eda, Technical Marketing, Debugging, Ddr, Axi, Arm Architecture
Brett Murdock Photo 31

Brett Murdock

Brett Murdock Photo 32

Tattoo Artist, Manager

Work:

Tattoo Artist, Manager
Brett Murdock Photo 33

Brett Murdock

Brett Murdock Photo 34

Brett Murdock - Wilton, IA

Work:
Musco Lighting Jun 2010 to 2000
Welder Menards - Iowa City, IA Mar 2007 to May 2010
Department Worker
Education:
University of Iowa - Iowa City, IA 2009
Bachelor's Muscatine Community College - Muscatine, IA 2006
Associates in Science in General Education Sr. High School - Wilton, IA 2004
High School Diploma

Publications & IP owners

Us Patents

Crossbar Switch That Supports A Multi-Port Slave Device And Method Of Operation

US Patent:
6954821, Oct 11, 2005
Filed:
Jul 31, 2003
Appl. No.:
10/631167
Inventors:
Michael D. Fitzsimmons - Austin TX, US
William C. Moyer - Dripping Springs TX, US
Brett W. Murdock - Round Rock TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
G06F013/00
US Classification:
710317, 710240
Abstract:
A crossbar switch () arbitrates for access from multiple bus masters (and ) to multiple addressed slave ports (and ) that have overlapping address ranges. In one form, the address ranges are the same address range. The crossbar switch () uses shared slave port control circuitry (), configuration registers () and slave port arbiter logic (and ) to arbitrate for access when all the addressed ports are busy. A determination is made as to whether new access requests are higher or lower in priority than existing accesses. A determination on where to direct a new access request is made based upon a prediction of which of certain multiple accesses will complete first based on various factors including the number of data beats requested as well as wait state information. In one mode, the wait state information is determined dynamically.

Arbiter Having Programmable Arbitration Points For Undefined Length Burst Accesses And Method

US Patent:
7013357, Mar 14, 2006
Filed:
Sep 12, 2003
Appl. No.:
10/660845
Inventors:
Brett W. Murdock - Round Rock TX, US
William C. Moyer - Dripping Springs TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
G06F 13/38
US Classification:
710240
Abstract:
An arbitration control circuit () for arbitrating access to a slave device () by a plurality of master devices () includes an undefined length burst (ULB) arbitration logic circuit (). The ULB arbitration logic circuit () includes a counter () and a control register (). The control register () stores a predetermined value. During a ULB access of the slave device (), the counter () is loaded with the predetermined value and is decremented for each beat of the undefined length burst access. Arbitration of the slave device (4) is only allowed after the predetermined number of access beats during the undefined length burst access.

Method And System For Accessing Memory Devices

US Patent:
7080191, Jul 18, 2006
Filed:
Dec 27, 2001
Appl. No.:
10/034834
Inventors:
Brett W. Murdock - Round Rock TX, US
Craig D. Shaw - Austin TX, US
Jeremy A. Jacobson - Bothell WA, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
G06F 12/00
US Classification:
711101, 711100
Abstract:
A system for accessing memory devices includes a processing module coupled to a set of outputs and memory operably coupled to the processing module. The memory stores operational instructions that cause the processing module to perform a plurality of operations. A first one of the plurality of operations includes utilizing a first output to provide a first data lane enable to facilitate accessing of a portion of a first memory storage location associated with a first memory address when in a first mode of operation. A second one of the plurality of operations includes utilizing the first output to provide an address bit of a second memory address to facilitate designation of a second memory storage location when in a second mode of operation.

Method And System Of Bus Master Arbitration

US Patent:
7099973, Aug 29, 2006
Filed:
Mar 26, 2003
Appl. No.:
10/402165
Inventors:
William C. Moyer - Dripping Springs TX, US
Michael D. Fitzsimmons - Austin TX, US
Brett W. Murdock - Round Rock TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
G06F 13/36
G06F 3/00
US Classification:
710118, 710 18, 710110, 710116
Abstract:
A system () having a plurality of bus masters () coupled to an arbiter () is disclosed. An arbiter () is coupled to a first storage location () and a second storage location (), where the first and second storage locations store bus master parking information for a system bus (). The arbiter () receives a parking context indicator () that is used to select one of the first and second storage locations () to provide bus master parking information to the arbiter ().

Processing System Having Sequential Address Indicator Signals

US Patent:
7124281, Oct 17, 2006
Filed:
Sep 21, 2000
Appl. No.:
09/667122
Inventors:
William C. Moyer - Dripping Springs TX, US
Jeffrey W. Scott - Austin TX, US
Brett W. Murdock - Austin TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
G06F 9/00
US Classification:
712205
Abstract:
Embodiments of the present inventions relate to processors having sequential address indicator signals, also referred to as sequence signals, for indicating when accessed addresses are sequential. One embodiment relates to a processing system for accessing memory having an address bus for providing a current address and a previous address to memory, a data bus, an execution unit, and a decode control unit. The processing system further includes a fetch unit, coupled to the execution unit, the decode control unit, the address bus, and the data bus, for generating a first sequence signal that when negated indicates that the current address may not be sequential to the previous address, a second sequence signal that when negated indicates that the current address is not sequential to the previous address, and a third sequence signal that when negated indicates that the current address, if it is an instruction address, is not sequential to the previous address that was an instruction address.

Data Processing System With Bus Access Retraction

US Patent:
7130943, Oct 31, 2006
Filed:
Sep 30, 2004
Appl. No.:
10/954809
Inventors:
William C. Moyer - Dripping Springs TX, US
Jimmy Gumulja - Austin TX, US
Brett W. Murdock - Round Rock TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
G06F 13/00
G06F 3/00
G06F 13/36
US Classification:
710107, 710 39, 710 40, 710 41, 710110, 710116, 710118
Abstract:
A bus master may selectively retract a currently pending access based on one or more characteristics of the currently pending access. In this manner, bus master may better control its access requests. The one or more characteristics may include, for example, type of access (e. g. read/write, instruction/data, burst/non-burst, etc. ), sequence or order of accesses, address being accessed (e. g. which address range is being accessed or which device is being accessed), the bus master requesting retraction (in an, e. g. , multimaster system), or any combination thereof. A bus arbiter may also selectively retract currently pending access requests in favor of a subsequent access request based on one or more characteristics of the currently pending access request or the subsequent access request. These characteristics may include any of those listed above, priorities of the requesting masters (e. g. a priority delta between requesting masters), other attributes of the requesting masters, or any combination thereof.

Method Of Accessing Memory Via Multiple Slave Ports

US Patent:
7185121, Feb 27, 2007
Filed:
Aug 15, 2005
Appl. No.:
11/203935
Inventors:
Michael D. Fitzsimmons - Austin TX, US
William C. Moyer - Dripping Springs TX, US
Brett W. Murdock - Round Rock TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
G06F 13/28
US Classification:
710 26, 710244, 710317
Abstract:
A crossbar switch () arbitrates for access from multiple bus masters ( and ) to multiple addressed slave ports ( and ) that have overlapping address ranges. In one form, the address ranges are the same address range. The crossbar switch () uses shared slave port control circuitry (), configuration registers () and slave port arbiter logic ( and ) to arbitrate for access when all the addressed ports are busy. A determination is made as to whether new access requests are higher or lower in priority than existing accesses. A determination on where to direct a new access request is made based upon a prediction of which of certain multiple accesses will complete first based on various factors including the number of data beats requested as well as wait state information. In one mode, the wait state information is determined dynamically.

Data Processing System With Bus Access Retraction

US Patent:
7340542, Mar 4, 2008
Filed:
Sep 30, 2004
Appl. No.:
10/955558
Inventors:
William C. Moyer - Dripping Springs TX, US
Brett W. Murdock - Round Rock TX, US
International Classification:
G06F 3/00
US Classification:
710 39, 710 40, 710 41, 710 42, 710 43, 710107, 710125, 710305
Abstract:
A bus master may selectively retract a currently pending access based on one or more characteristics of the currently pending access. In this manner, bus master may better control its access requests. The one or more characteristics may include, for example, type of access (e. g. read/write, instruction/data, burst/non-burst, etc. ), sequence or order of accesses, address being accessed (e. g. which address range is being accessed or which device is being accessed), the bus master requesting retraction (in an, e. g. , multimaster system), or any combination thereof. A bus arbiter may also selectively retract currently pending access requests in favor of a subsequent access request based on one or more characteristics of the currently pending access request or the subsequent access request. These characteristics may include any of those listed above, priorities of the requesting masters (e. g. a priority delta between requesting masters), other attributes of the requesting masters, or any combination thereof.

Possible Relatives

David Murdock  Dale E Murdock  Dana J Murdock  Dolores Murdock  Donna H Murdock  Doug V Murdock  Eileen N Murdock  Brett N White  Brett A Jones  Brett R Staples 

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