Brian J Abernethy, Age 546601 N 89Th Ln, Glendale, AZ 85305

Brian Abernethy Phones & Addresses

Glendale, AZ

337 Lewis Ave, Phoenix, AZ 85003 (480) 922-3759

Smithtown, NY

Spring Valley, NY

Scottsdale, AZ

Mentions for Brian J Abernethy

Brian Abernethy resumes & CV records

Resumes

Brian Abernethy Photo 28

Senior Financial Analyst

Location:
738 west Culver St, Phoenix, AZ 85007
Industry:
Commercial Real Estate
Work:
Institutional Property Advisors (Ipa)
Senior Financial Analyst
Marcus & Millichap Nov 1998 - Apr 2006
National Publications Manager
Education:
San Diego State University
Skills:
Real Estate Transactions, Brokerage, Real Estate, Location Intelligence, Real Estate Economics, Disposition, Shopping Centers, Property, Apartments, Leases
Brian Abernethy Photo 29

Brian Abernethy

Location:
16894 north Rosa Dr, Maricopa, AZ 85138
Industry:
Semiconductors
Work:
Applied Micro Circuits since Feb 2011
Principal Design Engineer
Symwave Mar 2009 - Apr 2010
Contractor
Sequoia Communications Jul 2003 - Apr 2009
Design Engineer
Applied Micro Circuits Corp Apr 1997 - May 2003
Design Engineer
Calcomp Apr 1979 - Sep 1996
Design Engineer
Education:
Devry University 1986 - 1986
BSEET, Electronics Technology
Skills:
Asic, Mixed Signal, Cmos, Analog, Pll, Ic, Testing, Soc, Semiconductors, Vco, Analog Circuit Design, Bicmos, Electronics, Rf, Microprocessors, Integrated Circuit Design, Radio Frequency, Phase Locked Loop, Integrated Circuits
Brian Abernethy Photo 30

Ldp Candidate

Work:
Api Group
Ldp Candidate
Brian Abernethy Photo 31

Brian Abernethy

Location:
Glendale, AZ
Work:
Glendale Community College
Education:
Glendale Community College
Brian Abernethy Photo 32

Brian Abernethy

Publications & IP owners

Us Patents

Noise-Canceling System For A Digitizing Tablet

US Patent:
4736073, Apr 5, 1988
Filed:
Feb 10, 1986
Appl. No.:
6/828060
Inventors:
Brian L. Abernethy - Glendale AZ
Assignee:
Sanders Associates, Inc. - Nashua NH
International Classification:
G08C 2100
US Classification:
178 19
Abstract:
A digitizing tablet (10) has common return lines (24, 25, 26, and 27) that tend to suppress sensing of the spurious signals induced in them when the digitizer probe (12) approaches the edge of a digitizing area (14). Each return line includes a connection segment (36) and a compensation segment (40), which extend in antiparallel along the edge of the digitizing area (14). The compensation segment (40) is spaced farther from the digitizing area than the connection segment (36) is so that it is only half as sensitive as the connection segment to probe signals. However, since only half of the emf induced in the connection segment (36) is coupled to the circuitry (22) for processing the induced signals, the signals induced in the return lines tend to cancel.

Digitizer System With Passive Pointer

US Patent:
5045645, Sep 3, 1991
Filed:
May 22, 1990
Appl. No.:
7/527027
Inventors:
Jason Hoendervoogt - Phoenix AZ
Brian Abernethy - Phoenix AZ
Assignee:
CalComp Inc. - Anaheim CA
International Classification:
G08C 2100
US Classification:
178 19
Abstract:
A driving grid is driven by an ac signal comprising a carrier frequency modulated by a lower frequency. An untethered, batteryless pointer includes a pick-up coil in a first tuned circuit tuned to the carrier frequency, connected by diodes to a driving coil in a second tuned circuit tuned to the lower modulating frequency. Energy picked up by the first tuned circuit from the driving grid at the carrier frequency drives the second tuned circuit at the modulating frequency. Modulating frequency signals induced in the receiving grid conductors are used to locate the pointer in the usual manner. Because the carrier signal contains no frequency component of the modulating signal, the driving grid and receiving grid are sufficiently decoupled.

Voltage Controlled Oscillator Circuit Employing Integrated Circuit Component Ratios

US Patent:
5384554, Jan 24, 1995
Filed:
Dec 8, 1993
Appl. No.:
8/163964
Inventors:
Brian Abernethy - Phoenix AZ
Assignee:
CalComp Inc. - Anaheim CA
International Classification:
H03K 303
US Classification:
331153
Abstract:
An integrated voltage controlled oscillator (VCO) circuit which utilizes the relative capacitance ratio between capacitors and the relative resistance ratio between resistors in an integrated circuit (IC) to output a signal having a predictable frequency for a given control signal voltage. The VCO output frequency will not vary more than 3. 0% from one IC chip implementing the VCO circuit, to the next. This low variance between IC chips is derived from the phenomenon whereby the respective ratios of capacitance and resistance between capacitors and resistors in the IC will not vary more than. +-. 1. 5% from the ratios of like capacitors and resistors on other IC chips. The integrated VCO circuit includes a control signal subcircuit, integrator subcircuit, filter subcircuit, and comparator unit subcircuit.

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