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Bruce A Tennant, Age 513141 13Th Ave, Beaverton, OR 97124

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Known as:
Bruce Allan Tennant Bruce Allen Tennant Bruce E Tennant
Related to:
Christopher K Tennant 53

Bruce Tennant Phones & Addresses

3141 13Th Ave, Hillsboro, OR 97124

Toledo, OH

551 32Nd St, Grand Rapids, MI 49548 (616) 272-3656

Maumee, OH

Comstock Park, MI

Portland, OR

Lansing, MI

Ypsilanti, MI

Honolulu, HI

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Work

Position: Administrative Support Occupations, Including Clerical Occupations

Education

Degree: High school graduate or higher

Emails

b***[email protected]

Mentions for Bruce A Tennant

Bruce Tennant resumes & CV records

Resumes

Bruce Tennant Photo 37

Adjunct Professor And Computer And Office Studies Department

Location:
Inglewood, CA
Industry:
Computer Software
Work:
Long Beach City College
Adjunct Professor and Computer and Office Studies Department Bruce Tennant
It Consultant - Transcription Long Beach City College Sep 1980 - Jun 1990
Adjunct Professor - Business Division
Education:
California State University, Long Beach 1980 - 1981
Cal State University Dominguez Hills 1976 - 1981
Bachelors, Bachelor of Arts, Psychology
Skills:
College Teaching, Public Speaking, Higher Education, Training, Research, Teaching, Distance Learning, Staff Development, Editing, Program Development, System Administration, Technical Support, It Strategy, Nonprofits, Community Outreach, Customer Service, Health Information Management, Active Directory, Testing, Strategic Planning, Social Networking, Event Planning, Regenerative Medicine
Interests:
Politics
Science and Technology
Education
Health
Languages:
English
Certifications:
License 12 9 Ten 002
California Community College Teaching Credential
The California Community Colleges, License 12 9 Ten 002
Bruce Tennant Photo 38

Principal Engineer - Enterprise Ip

Location:
Hillsboro, OR
Industry:
Semiconductors
Work:
Geocast Network Systems Jul 1999 - Mar 2001
Senior Design Engineer Advance Hardware Architectures 2001 - 2001
Senior Design Engineer Intel Corporation 2001 - 2001
Principal Engineer - Enterprise Ip
Education:
University of Michigan College of Engineering 1991 - 1996
Bachelors, Bachelor of Science, Computer Engineering, Engineering University of Michigan 1991 - 1996
Bachelor of Science In Engineering, Bachelors, Computer Engineering
Skills:
Logic Design, Pcie 3.0, Rtl Design, Systemverilog, Verilog, Vhdl, Perl, Static Timing Analysis, Simulation, Asic, Pcie, Soc, Modelsim, Fpga, Tcl, C, Digital Design, C++, Debugging, Computer Architecture, Logic Synthesis, Simulations, Application Specific Integrated Circuits, Field Programmable Gate Arrays, System on A Chip
Bruce Tennant Photo 39

Bruce Tennant

Publications & IP owners

Us Patents

Dynamic Squelch Detection Power Control

US Patent:
2010008, Apr 1, 2010
Filed:
Sep 29, 2008
Appl. No.:
12/286188
Inventors:
Sin Tan - Portland OR, US
Sivakumar Radhakrishnan - Portland OR, US
Bruce A. Tennant - Hillsboro OR, US
Jasper Balraj - Beaverton OR, US
Altug Koker - El Dorado Hills CA, US
International Classification:
H04B 1/10
US Classification:
455218
Abstract:
In one embodiment, the present invention includes power control logic for squelch detection circuitry to enable selective enabling of one or more squelch detection circuits of an interconnect interface in a low power mode. The logic may include a squelch mode control register to select a first mode or a second mode of power control, a second register coupled to the squelch mode control register to receive software settings to indicate which squelch detect circuit(s) to disable in a low power state of the interconnect, and a detector to dynamically detect a logical lane zero of the interconnect in the second mode. Other embodiments are described and claimed.

Squelch Filtration To Limit False Wakeups

US Patent:
2010033, Dec 30, 2010
Filed:
Jun 30, 2009
Appl. No.:
12/495697
Inventors:
Sin S. Tan - Portland OR, US
Srikanth T. Srinivasan - Portland OR, US
Bruce A. Tennant - Hillsboro OR, US
Dmitry Petrov - Ottawa, CA
International Classification:
G06F 1/32
US Classification:
713310
Abstract:
Methods and apparatus relating squelch filtration to limit false wakeups are described. In one embodiment, a squelch logic generates a wakeup event for an agent based on occurrence of a number of pulses (originating from another agent) during a time period. Other embodiments are also disclosed.

Recalibration Of Phy Circuitry For The Pci Express (Pipe) Interface Based On Using A Message Bus Interface

US Patent:
2022026, Aug 25, 2022
Filed:
May 6, 2022
Appl. No.:
17/738625
Inventors:
- Santa Clara CA, US
Minxi Gao - Chandler AZ, US
Debendra Das Sharma - Saratoga CA, US
Fulvio Spagna - San Jose CA, US
Bruce A. Tennant - Hillsboro OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 13/42
Abstract:
An interface couples a controller to a physical layer (PHY) block, where the interface includes a set of data pins comprising transmit data pins to send data to the PHY block and receive data pins to receive data from the PHY block. The interface further includes a particular set of pins to implement a message bus interface, where the controller is to send a write command to the PHY block over the message bus interface to write a value to at least one particular bit of a PHY message bus register, bits of the PHY message bus register are mapped to a set of control and status signals, and the particular bit is mapped to a recalibration request signal to request that the PHY block perform a recalibration.

Reduced Pin Count Interface

US Patent:
2021005, Feb 25, 2021
Filed:
Jul 6, 2020
Appl. No.:
16/921498
Inventors:
- Santa Clara CA, US
Dan Froelich - Portland OR, US
Debendra Das Sharma - Saratoga CA, US
Bruce Tennant - Hillsboro OR, US
Quinn Devine - Chandler AZ, US
Su Wei Lim - Penang, MY
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 13/42
G06F 13/38
G06F 13/40
Abstract:
An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.

Recalibration Of Phy Circuitry For The Pci Express (Pipe) Interface Based On Using A Message Bus Interface

US Patent:
2021003, Feb 4, 2021
Filed:
Jul 10, 2020
Appl. No.:
16/926524
Inventors:
- Santa Clara CA, US
Minxi Gao - Chandler AZ, US
Debendra Das Sharma - Saratoga CA, US
Fulvio Spagna - San Jose CA, US
Bruce A. Tennant - Hillsboro OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 13/42
Abstract:
An interface couples a controller to a physical layer (PHY) block, where the interface includes a set of data pins comprising transmit data pins to send data to the PHY block and receive data pins to receive data from the PHY block. The interface further includes a particular set of pins to implement a message bus interface, where the controller is to send a write command to the PHY block over the message bus interface to write a value to at least one particular bit of a PHY message bus register, bits of the PHY message bus register are mapped to a set of control and status signals, and the particular bit is mapped to a recalibration request signal to request that the PHY block perform a recalibration.

Flex Bus Protocol Negotiation And Enabling Sequence

US Patent:
2020021, Jul 2, 2020
Filed:
Mar 6, 2020
Appl. No.:
16/812156
Inventors:
- Santa Clara CA, US
Michelle C. Jen - Mountain View CA, US
Prahladachar Jayaprakash Bharadwaj - Bangalore, IN
Bruce A. Tennant - Hillsboro OR, US
Mahesh Wagh - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 13/40
G06F 13/42
Abstract:
Systems, methods, and devices can involve a host device that includes a root complex, a link, and an interconnect protocol stack coupled to a bus link. The interconnect protocol stack can include multiplexing logic to select one of a Peripheral Component Interconnect Express (PCIe) upper layer mode, or an accelerator link protocol upper layer mode, the PCIe upper layer mode or the accelerator link protocol upper layer mode to communicate over the link, and physical layer logic to determine one or more low latency features associated with one or both of the PCIe upper layer mode or the accelerator link protocol upper layer mode.

Enabling Sync Header Suppression Latency Optimization In The Presence Of Retimers For Serial Interconnect

US Patent:
2019038, Dec 19, 2019
Filed:
Aug 29, 2019
Appl. No.:
16/554974
Inventors:
Michelle Jen - Mountain View CA, US
Debendra Das Sharma - Saratoga CA, US
Bruce Tennant - Hillsboro OR, US
Prahladachar Jayaprakash Bharadwaj - Bangalore, IN
International Classification:
G06F 13/40
H04L 29/06
G06F 13/42
G06F 1/3237
Abstract:
Methods and apparatuses associated with a secure stream protocol for a serial interconnect are disclosed herein. In embodiments, an apparatus comprises a transmitter and a receiver. The transmitter and receiver are configured to transmit and receive transaction layer data packets through a link, the transaction layer data packets including indicators associated with transmission of order set transmitted after a predetermined number of data blocks, when the transmission is during a header suppression mode. Additional features and other embodiments are also disclosed.

Reduced Pin Count Interface

US Patent:
2019030, Oct 3, 2019
Filed:
Feb 4, 2019
Appl. No.:
16/266992
Inventors:
- Santa Clara CA, US
Daniel Froelich - Portland OR, US
Debendra Das Sharma - Saratoga CA, US
Bruce Tennant - Hillsboro OR, US
Quinn Devine - Chandler AZ, US
Su Wei Lim - Penang, MY
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 13/42
G06F 13/40
G06F 13/38
Abstract:
An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.

Isbn (Books And Publications)

Medical Transcription Power Building: Student Key And Guide

Author:
Bruce Tennant
ISBN #:
0894202227

Public records

Vehicle Records

Bruce Tennant

Address:
3141 NE 13 Ave, Hillsboro, OR 97124
Phone:
(503) 648-6214
VIN:
5FNRL5H91BB073705
Make:
HONDA
Model:
ODYSSEY
Year:
2011

Possible Relatives

Deborah A Tennant  Danielle D Tennant  Danny D Tennant  Dennis E Tennant  Don E Tennant  Elaine M Tennant  Eric D Tennant  Bruce B Johnston  Bruce J Joiner  Bruce E Stannard 

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