Chang S HaMenlo Park, CA

Chang Ha Phones & Addresses

Menlo Park, CA

Mentions for Chang S Ha

Professional Records

Medicine Doctors

Chang Ha Photo 1

Chang Young Ha

Specialties:
Physical Medicine & Rehabilitation
Spinal Cord Injury Medicine
Education:
Pusan National University (1973)

Resumes

Resumes

Chang Ha Photo 2

Chang Ha

Location:
San Francisco Bay Area
Industry:
Semiconductors
Chang Ha Photo 3

Chang Ha

Publications

Us Patents

Column Decoder With Increased Immunity To High Voltage Breakdown

US Patent:
6510084, Jan 21, 2003
Filed:
May 21, 2001
Appl. No.:
09/862277
Inventors:
Chang Wan Ha - Pleasanton CA
Assignee:
Winbond Electronics Corporation
International Classification:
G11C 1606
US Classification:
36518525, 36518529
Abstract:
A column decoder in an electrically-erasable, programmable read-only memory applies a bias voltage to, or floats, the gates of selected transistors during an erasure operation. This reduces the potential for gate oxide breakdown by decreasing the voltage difference between the gate and the relatively high erasure voltage. This allows the use of transistors having a thinner gate oxide, enabling easier laying out of the transistors within a given bit line pitch.

Controlling A Memory Device Responsive To Degradation

US Patent:
8320183, Nov 27, 2012
Filed:
Jan 27, 2011
Appl. No.:
13/015457
Inventors:
Chang Wan Ha - San Ramon CA,
Ramin Ghodsi - Cupertino CA,
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 11/34
US Classification:
36518517, 36518522, 36518529
Abstract:
Embodiments of the present invention disclosed herein include devices, systems and methods, such as those directed to non-volatile memory devices and systems capable of determining a degradation parameter associated with one or more memory cells. Disclosed devices and systems according to embodiments of the present invention include those that utilize the degradation parameter to adjust control signals coupled to the memory cells.

Program Method With Optimized Voltage Level For Flash Memory

US Patent:
7663934, Feb 16, 2010
Filed:
Nov 17, 2008
Appl. No.:
12/272281
Inventors:
Chang Wan Ha - San Ramon CA,
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 11/34
US Classification:
36518533, 36518517, 36518519, 36518522
Abstract:
A non-volatile memory device and programming process is described that increases the programming voltage of successive programming cycles in relation to the percentage of the data bits that failed programming verification during the previous programming cycle and were not correctly programmed into the memory array. This allows for a faster on average program operation and a more accurate match of the subsequent increase in the programming voltage to the non-volatile memory device, the specific region or row being programmed and any changes due to device wear. In one embodiment of the present invention the manufacturing process/design and/or specific memory device is characterized by generating a failed bit percentage to programming voltage increase profile to set the desired programming voltage delta/increase. In another embodiment of the present invention, methods and apparatus are related for the programming of data into non-volatile memory devices and, in particular, NAND and NOR architecture Flash memory.

Program Method With Optimized Voltage Level For Flash Memory

US Patent:
7876623, Jan 25, 2011
Filed:
Feb 16, 2010
Appl. No.:
12/706393
Inventors:
Chang Wan Ha - San Ramon CA,
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 11/34
US Classification:
36518533, 36518517, 36518519, 36518522
Abstract:
A non-volatile memory device and programming process is described that increases the programming voltage of successive programming cycles in relation to the percentage of the data bits that failed programming verification during the previous programming cycle and were not correctly programmed into the memory array. This allows for a faster on average program operation and a more accurate match of the subsequent increase in the programming voltage to the non-volatile memory device, the specific region or row being programmed and any changes due to device wear. In one embodiment of the present invention the manufacturing process/design and/or specific memory device is characterized by generating a failed bit percentage to programming voltage increase profile to set the desired programming voltage delta/increase. In another embodiment of the present invention, methods and apparatus are related for the programming of data into non-volatile memory devices and, in particular, NAND and NOR architecture Flash memory.

Controlling A Memory Device Responsive To Degradation

US Patent:
7894264, Feb 22, 2011
Filed:
Nov 7, 2007
Appl. No.:
11/983241
Inventors:
Chang Wan Ha - San Ramon CA,
Ramin Ghodsi - Cupertino CA,
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 11/34
US Classification:
36518517, 36518522, 36518529
Abstract:
Embodiments of the present invention disclosed herein include devices, systems and methods, such as those directed to non-volatile memory devices and systems capable of determining a degradation parameter associated with one or more memory cells. Disclosed devices and systems according to embodiments of the present invention include those that utilize the degradation parameter to adjust control signals coupled to the memory cells.

Method For Reading A Multilevel Cell In A Non-Volatile Memory Device

US Patent:
7917685, Mar 29, 2011
Filed:
May 4, 2006
Appl. No.:
11/417573
Inventors:
Chang Wan Ha - San Ramon CA,
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G06F 12/00
G06F 13/00
US Classification:
711103, 711100, 711118, 711154
Abstract:
A non-volatile memory device has a memory array comprising a plurality of memory cells. The array can operate in either a multilevel cell or single level cell mode and each cell has a lower page and an upper page of data. The memory device has a data latch for storing flag data and a cache latch coupled to the data latch. A read method comprises initiating a lower page read of a memory cell and reading, from the data latch, flag data that indicates whether a lower page read operation is necessary.

Charge Pump Operation In A Non-Volatile Memory Device

US Patent:
8000152, Aug 16, 2011
Filed:
Nov 30, 2009
Appl. No.:
12/627077
Inventors:
Chang Wan Ha - San Ramon CA,
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 16/06
US Classification:
36518525, 36518518, 36518909, 365226, 327536
Abstract:
A charge pump in a memory device is activated to produce a programming voltage prior to data loading during a programming operation. During an initial programming cycle, first and second load voltages are charged from the charge pump. The first load is removed from the charge pump during a verify operation. The first load voltage is subsequently recharged by charge sharing from the second load voltage so that the charge pump is not initially necessary for recharging the first load voltage.

Program And Sense Operations In A Non-Volatile Memory Device

US Patent:
8018770, Sep 13, 2011
Filed:
Nov 20, 2008
Appl. No.:
12/274508
Inventors:
Chang Wan Ha - San Ramon CA,
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 11/34
US Classification:
36518514, 36518528, 36518511
Abstract:
Methods for programming and sensing in a memory device, a data cache, and a memory device are disclosed. In one such method, all of the bit lines of a memory block are programmed or sensed during the same program or sense operation by alternately multiplexing the odd or even page bit lines to the dynamic data cache. The dynamic data cache is comprised of dual SDC, PDC, DDC1, and DDC2 circuits such that one set of circuits is coupled to the odd page bit lines and the other set of circuits is coupled to the even page bit lines.

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