Chang S HaMenlo Park, CA

6510084, Jan 21, 2003

May 21, 2001

09/862277

Chang Wan Ha - Pleasanton CA

Winbond Electronics Corporation

G11C 1606

36518525, 36518529

A column decoder in an electrically-erasable, programmable read-only memory applies a bias voltage to, or floats, the gates of selected transistors during an erasure operation. This reduces the potential for gate oxide breakdown by decreasing the voltage difference between the gate and the relatively high erasure voltage. This allows the use of transistors having a thinner gate oxide, enabling easier laying out of the transistors within a given bit line pitch.

6590810, Jul 8, 2003

Aug 15, 2001

09/930768

Chang Wan Ha - Pleasanton CA

Winbond Electronics Corporation - San Jose CA

G11C 1604

36518518, 36518505

A source biasing circuit for providing a negative biasing voltage to an electrically-erasable, programmable read-only memory (EEPROM) circuit during a read or programming operation. The negative biasing voltage helps overcome the source line resistance that would otherwise require a larger number of metal lines. The smaller number of metal lines required when using the source biasing circuit allows the EEPROM to be made smaller.

6704241, Mar 9, 2004

Sep 6, 2002

10/238048

Chang Wan Ha - Pleasanton CA

Winbond Electronics Corporation - Hsinchu

G11C 800

36523006, 36518511, 36518513

In accordance with an embodiment of the present invention, a semiconductor memory includes a memory array having a plurality of rows and columns of sectors, a horizontal global row decoder, a vertical global row decoder, and a plurality of horizontal local row decoders. Each of the sectors has a plurality of rows and columns of memory cells. The horizontal global row decoder is configured to select one of the rows of sectors in response to a first set of row address signals. The vertical global row decoder is configured to select one or two adjacent columns of the columns of sectors in response to a second set of row address signals. The plurality of horizontal local row decoders are coupled to the vertical global row decoder and the horizontal global row decoder to select one or two adjacent sectors located at the intersection of the selected row of sectors and the selected one or two adjacent columns of sectors.

6781914, Aug 24, 2004

Aug 23, 2001

09/938410

Chang Wan Ha - Pleasanton CA

Winbond Electronics Corp. - San Jose CA

G11C 700

36523003, 365 63, 36518904

A simultaneous operation flash memory chip architecture having a flexible memory bank partition for forming first and second memory banks from a plurality of flash memory arrays, said partition being defined by selecting one of a plurality of preformed metal masks, which allows the formation and extension of pre-decoded address lines to inputs of decoders associated with the first and second memory banks, respectively.

7005807, Feb 28, 2006

May 30, 2002

10/160921

Chang Chul Ha - San Jose CA, US
Lee Choon Rae - San Jose CA, US

cDream Corporation - San Jose CA

G09G 3/10

3151691, 3151693

An electron-emitting display device contains an emitter electrode, an anode and a gate electrode and an electron emission control device. The electron emission control device includes a plurality of voltage controllers which applies a positive voltage charge to the anode and emitter electrode respective. A third voltage controller applies a negative voltage charge to the gate inhibiting electron emission from electron emissive elements in the display device.

7009910, Mar 7, 2006

Jan 29, 2004

10/768398

Chang Wan Ha - Pleasanton CA, US

Winbond Electronics Corporation - Hsinchu

G11C 8/00

36523006, 36518511, 36518513, 36518523, 36523003

A semiconductor memory includes a plurality of memory array partitioned into first and second memory banks in correspondence with one of a plurality of mask options such that the first memory bank includes at least one but less than all of the plurality of memory arrays and the second memory bank includes a corresponding remainder of the plurality of memory arrays. A first horizontal global row decoder is configured to receive a first subset of addresses for the first memory bank and in response provide a first plurality of predecoded row address signals on a first plurality of lines extending only across the at least one but less than all of the plurality of memory arrays. A second horizontal global row decoder is configured to receive a first subset of addresses for the second memory bank and in response provide a second plurality of predecoded row address signals on a second plurality of lines extending only across the corresponding remainder of the plurality of memory arrays.

7053538, May 30, 2006

Feb 20, 2002

10/080012

Chang Chul Ha - San Jose CA, US
Kang Sung Gu - San Jose CA, US

cDream Corporation - San Jose CA

H01J 1/62

313309, 313495

An electron-emitting device contains an emitter resistor layer patterned into multiple laterally separated sections situated between the electron-emissive elements, on one hand, and emitter electrodes, on the other hand. Sections of the seed layer are spaced apart along each emitter electrode to electrically decouple electron emission elements disposed on the resistor layer.

7071603, Jul 4, 2006

Feb 20, 2002

10/080057

Chang Chul Ha - San Jose CA, US
Son Jong Woo - San Jose CA, US
Kim Jung Jae - San Jose CA, US

cDream Corporation - San Jose CA

H01J 1/62

313309, 313495

An electron-emitting device contains an emitter seed layer patterned into multiple laterally separated sections situated between the electron-emissive elements, on one hand, and emitter electrodes, on the other hand. Sections of the seed layer are spaced apart along each emitter electrode to electrically decouple electron emission elements disposed on the seed layer.