Chen A TianUnion City, CA

Chen Tian Phones & Addresses

Union City, CA

Palo Alto, CA

Fremont, CA

Mentions for Chen A Tian

Chen Tian resumes & CV records

Resumes

Chen Tian Photo 29

Multicore Researcher At Samsung R&D Center

Location:
San Francisco Bay Area
Industry:
Computer Software
Chen Tian Photo 30

Vice President Technical

Location:
Palo Alto, CA
Industry:
Telecommunications
Work:
Futurewei Technologies
Vice President Technical
Futurewei Technologies Apr 2015 - Apr 2017
Director and Software Architect
Futurewei Technologies Dec 2012 - Mar 2015
Principal Engineer
Samsung Electronics Jan 2012 - Dec 2012
Staff Research Engineer
Samsung Electronics Jul 2010 - Dec 2011
Senior Research Engineer
Education:
University of California, Riverside 2007 - 2010
PhD, Computer Science
University of Arizona 2005 - 2007
Master, Computer Science
Skills:
Operating Systems, Software Engineering, C++, Distributed Systems, Computer Science, Parallel Computing, Java, C, Compilers, Architecture, Runtimes, Architectures, Computer Architecture, Parallel Programming, Programming Languages, Compiler, Distributed Computing, Heterogeneous Computing, Ai Framework

Publications & IP owners

Us Patents

Numa Aware System Task Management

US Patent:
2012010, Apr 26, 2012
Filed:
Mar 31, 2011
Appl. No.:
13/077612
Inventors:
Daniel WADDINGTON - Morgan Hill CA, US
Chen TIAN - Fremont CA, US
Assignee:
SAMSUNG ELECTRONICS CO., LTD. - Suwon City
International Classification:
G06F 9/46
US Classification:
718104, 718102
Abstract:
Task management in a Non-Uniform Memory Access (NUMA) architecture having multiple processor cores is aware of the NUMA topology in task management. As a result memory access penalties are reduced. Each processor is assigned to a zone allocated to a memory controller. The zone assignment is based on a cost function. In a default mode a thread of execution attempts to perform work in a queue of the same zone as the processor to minimize memory access penalties. Additional work stealing rules may be invoked if there is no work for a thread to perform from its default zone queue.

Adaptive Queuing Methodology For System Task Management

US Patent:
2012010, Apr 26, 2012
Filed:
Mar 31, 2011
Appl. No.:
13/077567
Inventors:
Daniel WADDINGTON - Morgan Hill CA, US
Chen TIAN - Fremont CA, US
Assignee:
SAMSUNG ELECTRONICS CO., LTD. - Suwon City
International Classification:
G06F 9/46
US Classification:
718105
Abstract:
A task management methodology for system having multiple processors and task queues adapts a queuing topology by monitoring a queue pressure and adjusting the queue topology from a selection of at least two different queue topologies. The queue pressure may be periodically monitored and queues with different granularities selected. The methodology reduced contention when there is high pressure on the queues while also reducing overhead to manage queues when there is less pressure on the queues.

Prevention Of Race Conditions In Library Code Through Memory Page-Fault Handling Mechanisms

US Patent:
2013004, Feb 14, 2013
Filed:
Mar 20, 2012
Appl. No.:
13/425312
Inventors:
Daniel G. WADDINGTON - Morgan Hill CA, US
Chen TIAN - Union City CA, US
Tongping LIU - Amherst MA, US
Assignee:
SAMSUNG ELECTRONICS CO., LTD. - Suwon City
International Classification:
G06F 12/14
US Classification:
711152, 711E12102
Abstract:
Protection of shared data in a multi-core processing environment is disclosed. A page-fault handling mechanism is adapted to synchronize access to shared memory. An application of the present invention is for synchronizing access to potentially shared data, where the shared data is opaque in that it does not have a well-defined structure.

Coupled Lock Allocation And Lookup For Shared Data Synchronization In Symmetric Multithreading Environments

US Patent:
2013004, Feb 21, 2013
Filed:
Feb 29, 2012
Appl. No.:
13/408263
Inventors:
Daniel WADDINGTON - Morgan Hill CA, US
Tongping Liu - Amherst MA, US
Chen Tian - Fremont CA, US
Assignee:
Samsung Electronics Co., Ltd. - Suwon City
International Classification:
G06F 12/14
US Classification:
711152, 711E12094
Abstract:
In a shared memory process different threads may attempt to access a shared data variable in a shared memory. Locks are provided to synchronize access to shared data variables. Each lock is allocated to have a location in the shared memory relative to the instance of shared data that the lock protects. A lock may be allocated to be adjacent to the data that it protects. Lock resolution is facilitated because the memory location of a lock can be determined from an offset with respect to the data variable that is being protected by the lock.

Scalable, Customizable, And Load-Balancing Physical Memory Management Scheme

US Patent:
2013023, Sep 5, 2013
Filed:
Mar 2, 2012
Appl. No.:
13/411148
Inventors:
Chen TIAN - Union City CA, US
Daniel G. WADDINGTON - Morgan Hill CA, US
Assignee:
Samsung Electronics Co., Ltd. - Suwon City
International Classification:
G06F 12/02
US Classification:
711170, 711E12059, 711E12002
Abstract:
A physical memory management scheme for handling page faults in a multi-core or many-core processor environment is disclosed. A plurality of memory allocators is provided. Each memory allocator may have a customizable allocation policy. A plurality of pagers is provided. Individual threads of execution are assigned a pager to handle page faults. A pager, in turn, is bound to a physical memory allocator. Load balancing may also be provided to distribute physical memory resources across allocators. Allocations may also be NUMA-aware.

Scalable And Secure Application Resource Management And Access Control For Multicore Operating Systems

US Patent:
2013028, Oct 24, 2013
Filed:
Oct 9, 2012
Appl. No.:
13/648157
Inventors:
- Suwon City, KR
Chen TIAN - Union City CA, US
Assignee:
SAMSUNG ELECTRONICS CO., LTD. - Suwon City
International Classification:
G06F 21/00
US Classification:
726 17
Abstract:
An architecture for multi-core and many-core processor systems includes a set of resource managers having a hierarchy of at least one level. The resource managers act as trusted proxies for the operating system (OS) kernel to manage resources for applications. The application may include a trusted secure specification defining resource and access privileges of the associated application.

Distributed Resource Management By Improving Cluster Diversity

US Patent:
2021027, Sep 2, 2021
Filed:
May 6, 2021
Appl. No.:
17/302585
Inventors:
- Shenzhen, CN
Zongfang Lin - Santa Clara CA, US
Chen Tian - Palo Alto CA, US
Ziang Hu - Union City CA, US
International Classification:
H04L 29/08
Abstract:
A method of distributed resource management in a distributed computing system includes determining usage of respective hardware resources by an application and generating usage metrics for the application, and assigning the application to a cluster of hardware resources to optimize diversity of usage of hardware resources in the cluster and to enhance utilization of the hardware resources by applications running in that cluster. The diversity of usage of the hardware resources is determined from respective usage metrics of the respective applications running in that cluster. The diversity of usage of the hardware resources in the cluster is optimized by assigning the application to a diversity pool of hardware resources adapted to minimize interference when applications assigned to the diversity pool of hardware resources access the hardware resources in the diversity pool and assigning applications from different diversity pools to the cluster of hardware resources.

Model Checker For Finding Distributed Concurrency Bugs

US Patent:
2019033, Oct 31, 2019
Filed:
Apr 25, 2018
Appl. No.:
15/962873
Inventors:
- Plano TX, US
- Chicago IL, US
Haryadi Gunawi - Chicago IL, US
Feng Ye - Mississauga, CA
Chen Tian - Union City CA, US
Shen Chi Chen - San Jose CA, US
International Classification:
G06F 11/36
Abstract:
Described herein are systems and methods for distributed concurrency (DC) bug detection. The method includes identifying a plurality of nodes in a distributed computing cluster; identifying a plurality of messages to be transmitted during execution of an application by the distributed computing cluster; determining a set of orderings of the plurality of messages for DC bug detection, the set of orderings determined based upon the plurality of nodes and the plurality of messages; removing a subset of the orderings from the set of orderings based upon one or more of a state symmetry algorithm, a disjoint-update independence algorithm, or a zero-crash-impact reordering algorithm; and performing DC bug detection testing using the set of orderings after the subset of the orderings is removed from the set of orderings.

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