Chris Henry Simon, Age 613446 44Th Ave S, Minneapolis, MN 55406

Chris Simon Phones & Addresses

3446 44Th Ave S, Minneapolis, MN 55406 (612) 724-8947

3448 44Th Ave S, Minneapolis, MN 55406

Austin, TX

Saint Paul, MN

Work

Company: Target corporation - Edina, MN Mar 2005 Position: Store manager

Education

School / High School: Univeristy of Minnesota- Minneapolis, MN 1983 Specialities: BS in Geography

Mentions for Chris Henry Simon

Chris Simon resumes & CV records

Resumes

Chris Simon Photo 52

Chris Simon - Brooklyn Park, MN

Work:
Target Corporation - Edina, MN Mar 2005 to Apr 2014
Store Manager
Education:
Univeristy of Minnesota - Minneapolis, MN 1983 to 1989
BS in Geography

Publications & IP owners

Us Patents

Methods For Filling Holes In Printed Wiring Boards

US Patent:
7802360, Sep 28, 2010
Filed:
Jan 28, 2004
Appl. No.:
10/765201
Inventors:
Deepak Keshav Pai - Burnsville MN, US
Chris H. Simon - Minneapolis MN, US
Assignee:
General Dynamics Advanced Information Systems, Inc. - Fairfax VA
International Classification:
H01K 3/10
US Classification:
29852, 29846, 216 18, 427 971, 427 977
Abstract:
The invention comprises methods for filling holes in printed wiring boards and printed wiring boards produced by these methods. The methods involve plating metal conductors inside the holes of the printed wiring boards while protecting the conducting surfaces of the printed wiring boards from being plated using photoresist film. The side surfaces of a printed wiring board are covered with photoresist. The photoresist is exposed to developing light, except the photoresist covering the holes on one side of the board is masked to prevent exposure of the holes to the developing light. The undeveloped photoresist covering the holes is removed. The board is subjected to a plating process, which deposits conductive materials in the holes, but the photoresist on the conducting surfaces of the board prevents conductive materials to be plated on the surfaces of the board.

Method And Apparatus For Adjusting The Clock Delay In Systems With Multiple Integrated Circuits

US Patent:
2003002, Feb 6, 2003
Filed:
Mar 2, 2001
Appl. No.:
09/798155
Inventors:
Ronald Denny - Brooklyn Center MN, US
Chris Simon - Minneapolis MN, US
Joan Zak - Savage MN, US
International Classification:
H04L007/00
US Classification:
375/354000
Abstract:
An apparatus and method for adjusting the clock delay in systems with multiple integrated circuits has a controller, a programmable clock generator and a plurality of integrated circuits, each integrated circuit including a data flip-flop, a programmable delay and a clock-fanout tree, wherein the clock delay in the integrated circuits is adjusted to match the inherent delay in the integrated circuit having the longest inherent delay.

Methods For Filling Holes In Printed Wiring Boards

US Patent:
2011006, Mar 24, 2011
Filed:
Aug 18, 2010
Appl. No.:
12/805753
Inventors:
Deepak Keshav Pai - Burnsville MN, US
Chris H. Simon - Minneapolis MN, US
Assignee:
General Dynamics Advanced Information Systems, Inc - Fairfax VA
International Classification:
H01K 3/10
US Classification:
29852
Abstract:
The invention comprises methods for filling holes in printed wiring boards and printed wiring boards produced by these methods. The methods involve plating metal conductors inside the holes of the printed wiring boards while protecting the conducting surfaces of the printed wiring boards from being plated using photoresist film. The side surfaces of a printed wiring board are covered with photoresist. The photoresist is exposed to developing light, except the photoresist covering the holes on one side of the board is masked to prevent exposure of the holes to the developing light. The undeveloped photoresist covering the holes is removed. The board is subjected to a plating process, which deposits conductive materials in the holes, but the photoresist on the conducting surfaces of the board prevents conductive materials to be plated on the surfaces of the board.

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