Christopher J Phoenix, Age 54604 N Genevieve Ln, San Jose, CA 95128

2019016, May 30, 2019

Nov 28, 2017

15/824744

- Mountain View CA, US
Christopher J. Phoenix - Mountain View CA, US

Google LLC - Mountain View CA

G06F 1/32
G06F 12/0811
G06F 12/0831
G06F 12/0804

Techniques and apparatuses are described that enable power-conserving cache memory usage. Main memory constructed using, e.g., DRAM can be placed in a low-power mode, such as a self-refresh mode, for longer time periods using the described techniques and apparatuses. A hierarchical memory system includes a supplemental cache memory operatively coupled between a higher-level cache memory and the main memory. The main memory can be placed in the self-refresh mode responsive to the supplemental cache memory being selectively activated. The supplemental cache memory can be implemented with a highly- or fully-associative cache memory that is smaller than the higher-level cache memory. Thus, the supplemental cache memory can handle those cache misses by the higher-level cache memory that arise because too many memory blocks are mapped to a single cache line. In this manner, a DRAM implementation of the main memory can be kept in the self-refresh mode for longer time periods.