Clement Tse resumes & CV records
Resumes
Clement Tse
Clement Tse
Location:
San Francisco Bay Area
Industry:
Semiconductors
Clement C Tse, Age 61681 Upper Vintners Cir, Fremont, CA 94539
Clement Tse Phones & Addresses
Fremont, CA
Alameda, CA
Mentions for Clement C Tse
Publications & IP owners
Us Patents
System And Method For Managing The Design And Configuration Of An Integrated Circuit Semiconductor Design
US Patent:
8103987, Jan 24, 2012
Filed:
Mar 9, 2007
Appl. No.:
11/684156
Inventors:
Soumya Banerjee - San Jose CA, US
Todd Michael Bezenek - San Jose CA, US
Clement Tse - Fremont CA, US
Todd Michael Bezenek - San Jose CA, US
Clement Tse - Fremont CA, US
Assignee:
MIPS Technologies, Inc. - Sunnyvale CA
International Classification:
G06F 17/50
US Classification:
716100
Abstract:
A system and methods that facilitate the design process and minimize the time and effort required to complete the design and fabrication of an integrated circuits (IC) are described. The system and method utilize a plurality of repositories, rules engines and design and verification tools to analyze the workload and automatically produce a hardened GDSII description or other representation of the device. The system and method securely maintains synthesizable RTL on a server in a data center while providing designers access to portions of the mechanism by way of a network portal.
Methods And Systems For Measuring And Presenting Performance Data Of A Memory Controller System
US Patent:
8499201, Jul 30, 2013
Filed:
Jul 22, 2010
Appl. No.:
12/841762
Inventors:
Gordon Raymond Chiu - Richmond Hill, CA
Joshua David Fender - East York, CA
Clement C. Tse - Fremont CA, US
Deshanand Singh - Mississauga, CA
Joshua David Fender - East York, CA
Clement C. Tse - Fremont CA, US
Deshanand Singh - Mississauga, CA
Assignee:
Altera Corporation - San Jose CA
International Classification:
G06F 11/00
US Classification:
714 46, 714 42
Abstract:
Mechanisms for measuring, analyzing, and presenting performance data associated with a memory controller system are described. The mechanisms include a performance monitor that detects and analyzes performance including efficiency and latency of a memory controller system. In addition to determining performance, the systems identifies reasons for loss of memory controller system efficiency. Moreover, the reasons, the efficiency, and the latency are analyzed and presented in a manner easily understandable to a user.
Remote Interface For Managing The Design And Configuration Of An Integrated Circuit Semiconductor Design
US Patent:
2008022, Sep 11, 2008
Filed:
Mar 9, 2007
Appl. No.:
11/684189
Inventors:
Soumya Banerjee - San Jose CA, US
Todd Michael Bezenek - San Jose CA, US
Clement Tse - Fremont CA, US
Todd Michael Bezenek - San Jose CA, US
Clement Tse - Fremont CA, US
Assignee:
MIPS TECHNOLOGIES, INC. - Mountain View CA
International Classification:
G06F 17/50
US Classification:
716 4
Abstract:
A software system for facilitating the design process and minimizing the time and effort required to complete the design and fabrication of an integrated circuits (IC) is described. The software system utilizes a data center having a plurality of repositories, rules engines and design and verification tools to automatically produce a hardened GDSII description or other representation of the device in response to the formation of a electronic license agreement. Designers select contractual terms for incorporating third party intellectual property and then design and initiate manufacture of the IC by way of a network portal.
Real Time Programmable Chroma Keying With Shadow Generation
US Patent:
7006155, Feb 28, 2006
Filed:
Feb 1, 2000
Appl. No.:
09/495540
Inventors:
Vinay Agarwala - San Jose CA, US
Clement Tse - Fremont CA, US
Clement Tse - Fremont CA, US
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
H04N 9/75
US Classification:
348592, 348598, 348597
Abstract:
A system for forming composite video images from one or more foreground images and one or more background images. In one embodiment, s sum of a suppressed foreground image signal with weight α, with one or more selected foreground colors suppressed, and a background image signal with weight 1−α′ (0≦α′≦1) is formed, where a and α′ may vary from pixel to pixel and with time. In another embodiment, a shadow from a selected foreground image is impressed on selected pixels of a background image. In another embodiment, foreground suppression and shadowing are combined, optionally by retrofitting, using an existing α-mixer or a newly constructed α-mixer. Provision of a chroma key map allows a foreground image shadow to be prescribed pixel by pixel, including a transition region in which the shadowed image slowly disappears.
Systems And Methods For Creating An Integrated Circuit With A Remote Device
US Patent:
2019039, Dec 26, 2019
Filed:
Aug 12, 2019
Appl. No.:
16/538107
Inventors:
- Cambridge, GB
Todd Michael Bezenek - San Jose CA, US
Clement Tse - Fremont CA, US
Todd Michael Bezenek - San Jose CA, US
Clement Tse - Fremont CA, US
International Classification:
G06Q 30/06
G06F 17/50
G06Q 50/18
G06F 17/50
G06Q 50/18
Abstract:
Systems and methods for using logic design processing to create an integrated circuit (IC). A method for creating an IC with a client device that is configured to perform all of the steps of receiving technology options and operating system options for the IC, selecting one of the technology options and one of the operating system options, receiving a subset of processor cores matching the selected technology option and the selected operating system option, identifying a particular processor core from among the subset of processor cores, customizing the particular processor core by adjusting at least one of default values for a system clock, a memory configuration, or a cache value based on the selected technology option to create a customized processor core configuration, presenting the customized processor core configuration in a graphical format and, in response, confirming the customized processor core configuration as a desired core configuration to be built, and sending device instructions to build an IC based on the desired core configuration.
Computer-Aided Design Of Integrated Circuits
US Patent:
2015015, Jun 4, 2015
Filed:
Feb 9, 2015
Appl. No.:
14/616982
Inventors:
- Cambridge, GB
Todd Michael Bezenek - San Jose CA, US
Clement Tse - Fremont CA, US
Todd Michael Bezenek - San Jose CA, US
Clement Tse - Fremont CA, US
International Classification:
G06Q 30/06
G06F 17/50
G06Q 50/18
G06F 17/50
G06Q 50/18
Abstract:
A software system for facilitating the design process and minimizing the time and effort required to complete the design and fabrication of an integrated circuits (IC) is described. The software system utilizes a data center having a plurality of repositories, rules engines and design and verification tools to automatically produce a hardened GDSII description or other representation of the device in response to the formation of a electronic license agreement. Designers select contractual terms for incorporating third party intellectual property and then design and initiate manufacture of the IC by way of a network portal.
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