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Craig Edward Core, Age 64143 Thistle Rd, North Andover, MA 01845

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Known as:
Craig E Core Craig Z Core Edward C Core Carole Core Edward C Stanger
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Edward C Stanger 86

Craig Core Phones & Addresses

143 Thistle Rd, North Andover, MA 01845 (978) 682-3831

32 Hollowtree Ln, North Andover, MA 01845 (978) 682-3831

Blawnox, PA

Sewickley, PA

Essex, MA

32 Hollow Tree Ln, Methuen, MA 01844 (978) 682-3831

Somerville, MA

Framingham, MA

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Craig Edward Core

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Work

Company: Qualtré inc. 2009 to 2014 Position: Vice president of operations

Education

Degree: Master of Business Administration, Masters School / High School: Northeastern University 1999 to 2002

Skills

Semiconductors • Manufacturing • Mems • Electronics • Design of Experiments • Spc • Process Engineering • Engineering • Engineering Management • Cross Functional Team Leadership • Failure Analysis • Product Development • Sensors • Semiconductor Industry • Testing • Silicon • Statistical Process Control • Ic • Root Cause Analysis • Start Ups • Yield • Cmos • Process Simulation • R&D • Six Sigma • Thin Films • Electrical Engineering • Design For Manufacturing • Lean Manufacturing • Quality Management • Product Engineering • Pcb Design • Solar Energy • Supply Chain • Mixed Signal • Rf • Analog • Characterization • Metrology • Optics • Fmea • Integrated Circuits • Simulations • Labview • Test Engineering • Dmaic • Radio Frequency

Industries

Electrical/Electronic Manufacturing

Mentions for Craig Edward Core

Craig Core resumes & CV records

Resumes

Craig Core Photo 19

Vice President Of Engineering And Operations

Location:
North Andover, MA
Industry:
Electrical/Electronic Manufacturing
Work:
Qualtré Inc. 2009 - 2014
Vice President of Operations Vesper Mems 2009 - 2014
Vice President of Engineering and Operations Evergreen Solar 2007 - 2009
Plant Manager Analog Devices 1986 - 2007
Wafer Fab Manager National Semiconductor 1983 - 1986
Product Engineer
Education:
Northeastern University 1999 - 2002
Master of Business Administration, Masters Northeastern University 1988 - 1991
Master of Business Administration, Masters Penn State University 1979 - 1983
Bachelors, Bachelor of Science
Skills:
Semiconductors, Manufacturing, Mems, Electronics, Design of Experiments, Spc, Process Engineering, Engineering, Engineering Management, Cross Functional Team Leadership, Failure Analysis, Product Development, Sensors, Semiconductor Industry, Testing, Silicon, Statistical Process Control, Ic, Root Cause Analysis, Start Ups, Yield, Cmos, Process Simulation, R&D, Six Sigma, Thin Films, Electrical Engineering, Design For Manufacturing, Lean Manufacturing, Quality Management, Product Engineering, Pcb Design, Solar Energy, Supply Chain, Mixed Signal, Rf, Analog, Characterization, Metrology, Optics, Fmea, Integrated Circuits, Simulations, Labview, Test Engineering, Dmaic, Radio Frequency

Publications & IP owners

Us Patents

Method Of Forming A Cover Cap For Semiconductor Wafer Devices

US Patent:
6352935, Mar 5, 2002
Filed:
Jan 18, 2000
Appl. No.:
09/484991
Inventors:
David J. Collins - Windham NH
Craig E. Core - North Andover MA
Lawrence E. Felton - Hopkinton MA
Jing Luo - Lexington MA
Assignee:
Analog Devices, Inc. - Norwood MA
International Classification:
H01L 21302
US Classification:
438708, 438118
Abstract:
A method for capping active areas of a semiconductor wafer uses photolithography to define areas of sealant on the cap wafer to thereby reduce the amount of space required for attaching the cap wafer to the semiconductor wafer carrying active areas to be capped. Using photolithography in this manner increases the amount of space on the semiconductor wafer that can be used to form active areas which, in turn, improves the density of active area on the semiconductor wafer. In one embodiment, the method includes the steps of applying a photoimageable layer, photoimaging the photoimageable layer to define a pattern including remaining regions of the photoimageable layer and removed regions of the photoimageable layer, and using the pattern to define the sealant regions on the semiconductor wafer. The method may further include one or more steps, such as applying sealant to the sealant regions defined by the pattern, curing the sealant, removing the remaining regions after applying the sealant to the sealant regions, removing excess sealant not within the sealant regions, and using the sealant material to form at least one seal around at least one active area formed on the second semiconductor substrate.

Flow Sensor Chip

US Patent:
7703339, Apr 27, 2010
Filed:
Dec 8, 2006
Appl. No.:
11/636376
Inventors:
Craig E. Core - North Andover MA, US
Assignee:
Analog Devices, Inc. - Norwood MA
International Classification:
G01P 5/06
US Classification:
7386185
Abstract:
A flow sensor has an inlet chamber with a first pressure sensor and an inlet port for receiving fluid, and an outlet chamber with a second pressure sensor and an outlet port. The flow sensor also has an anemometer in fluid communication with at least one of the two chambers.

Micromachined Microphone And Multisensor And Method For Producing Same

US Patent:
7825484, Nov 2, 2010
Filed:
Apr 25, 2005
Appl. No.:
11/113925
Inventors:
John R. Martin - Foxborough MA, US
Timothy J. Brosnihan - Natick MA, US
Craig Core - North Andover MA, US
Thomas Kieran Nunan - Carlisle MA, US
Jason Weigold - Somerville MA, US
Xin Zhang - Acton MA, US
Assignee:
Analog Devices, Inc. - Norwood MA
International Classification:
H01L 29/82
US Classification:
257415, 257704, 257419, 257680, 257E21235, 257E31032, 381191, 381175, 381355
Abstract:
A micromachined microphone is formed from a silicon or silicon-on-insulator (SOI) wafer. A fixed sensing electrode for the microphone is formed from a top silicon layer of the wafer. Various polysilicon microphone structures are formed above a front side of the top silicon layer by depositing at least one oxide layer, forming the structures, and then removing a portion of the oxide underlying the structures from a back side of the top silicon layer through trenches formed through the top silicon layer. The trenches allow sound waves to reach the diaphragm from the back side of the top silicon layer. In an SOI wafer, a cavity is formed through a bottom silicon layer and an intermediate oxide layer to expose the trenches for both removing the oxide and allowing the sound waves to reach the diaphragm. An inertial sensor may be formed on the same wafer, with various inertial sensor structures formed at substantially the same time and using substantially the same processes as corresponding microphone structures.

Micromachined Microphone And Multisensor And Method For Producing Same

US Patent:
8129803, Mar 6, 2012
Filed:
Jul 16, 2010
Appl. No.:
12/804213
Inventors:
John R. Martin - Foxborough MA, US
Timothy J. Brosnihan - Natick MA, US
Craig Core - North Andover MA, US
Thomas Kieran Nunan - Carlisle MA, US
Jason Weigold - Newburyport MA, US
Xin Zhang - Acton MA, US
Assignee:
Analog Devices, Inc. - Norwood MA
International Classification:
H01L 21/02
H01L 21/84
US Classification:
257415, 257416, 257E21002, 257E2932, 438 53, 438E21704, 438400, 438 48, 438 52
Abstract:
A micromachined microphone is formed from a silicon or silicon-on-insulator (SOI) wafer. A fixed sensing electrode for the microphone is formed from a top silicon layer of the wafer. Various polysilicon microphone structures are formed above a front side of the top silicon layer by depositing at least one oxide layer, forming the structures, and then removing a portion of the oxide underlying the structures from a back side of the top silicon layer through trenches formed through the top silicon layer. The trenches allow sound waves to reach the diaphragm from the back side of the top silicon layer. In an SOI wafer, a cavity is formed through a bottom silicon layer and an intermediate oxide layer to expose the trenches for both removing the oxide and allowing the sound waves to reach the diaphragm. An inertial sensor may be formed on the same wafer, with various inertial sensor structures formed at substantially the same time and using substantially the same processes as corresponding microphone structures.

Method Of Forming A Self-Aligned Capacitor

US Patent:
5480831, Jan 2, 1996
Filed:
Mar 15, 1995
Appl. No.:
8/404314
Inventors:
Craig E. Core - North Andover MA
Assignee:
Analog Devices, Inc. - Wilmington MA
International Classification:
H01L 2170
H01L 2700
US Classification:
437 60
Abstract:
A self-aligned capacitor structure and method of making it includes an insulating support substrate with the capacitor disposed on the insulating substrate with a first conducting extending across the capacitor in the first dimension. The capacitor includes a first electrode interconnected with the first conductor, a second electrode supported by the substrate and interconnected with the second conductor, and a dielectric medium between the first and second electrodes. The first and second electrodes being coterminous in both directions in the first dimension for eliminating parasitic capacitance between the first conductor and the second electrode.

Possible Relatives

Deborah L Core  Denise Core  Edward N Core  Gary Core  George P Core  Harvey L Core  James J Core  Craig Standish  Craig L White  Craig M Stanley 

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