Dale Laird Hetherington, Age 74Tucson, AZ

6808952, Oct 26, 2004

Sep 5, 2002

10/236631

Jeffry J. Sniegowski - Albuquerque NM
Thomas W. Krygowski - Cortlandt Manon NY
Seethambal S. Mani - Albuquerque NM
Scott D. Habermehl - Corrales NM
Dale L. Hetherington - Albuquerque NM
James E. Stevens - Albuquerque NM
Paul J. Resnick - Albuquerque NM
Steven R. Volk - Albuquerque NM

Sandia Corporation - Albuquerque NM

H01L 2100

438 48, 438 50, 438 53

A process is disclosed for forming a microelectromechanical (MEM) structure on a substrate having from 5 to 6 or more layers of deposited and patterned polysilicon. The process is based on determining a radius of curvature of the substrate which is bowed due to accumulated stress in the layers of polysilicon and a sacrificial material used to buildup the MEM structure, and then providing one or more stress-compensation layers on a backside of the substrate to flatten the substrate and allow further processing.

7004198, Feb 28, 2006

Jul 20, 2004

10/894636

Murat Okandan - Albuquerque NM, US
Paul C. Galambos - Albuquerque NM, US
Gilbert L. Benavides - Los Ranchos NM, US
Dale L. Hetherington - Albuquerque NM, US

Sandia Corporation - Albuquerque NM

F16K 37/00

137827, 137554, 137833, 204601, 251368

An apparatus for simultaneously aligning and interconnecting microfluidic ports is presented. Such interconnections are required to utilize microfluidic devices fabricated in Micro-Electromechanical-Systems (MEMS) technologies, that have multiple fluidic access ports (e. g. 100 micron diameter) within a small footprint, (e. g. 3 mm×6 mm). Fanout of the small ports of a microfluidic device to a larger diameter (e. g. 500 microns) facilitates packaging and interconnection of the microfluidic device to printed wiring boards, electronics packages, fluidic manifolds etc.

5998298, Dec 7, 1999

Apr 28, 1998

9/067614

James G. Fleming - Albuquerque NM
Dale L. Hetherington - Albuquerque NM
Bradley K. Smith - Edgewood NM

Sandia Corporation - Albuquerque NM

H01L 3300

438692

A method is disclosed for fabricating a two- or three-dimensional photonic bandgap structure (also termed a photonic crystal, photonic lattice, or photonic dielectric structure). The method uses microelectronic integrated circuit (IC) processes to fabricate the photonic bandgap structure directly upon a silicon substrate. One or more layers of arrayed elements used to form the structure are deposited and patterned, with chemical-mechanical polishing being used to planarize each layer for uniformity and a precise vertical tolerancing of the layer. The use of chemical-mechanical planarization allows the photonic bandgap structure to be formed over a large area with a layer uniformity of about two-percent. Air-gap photonic bandgap structures can also be formed by removing a spacer material separating the arrayed elements by selective etching. The method is useful for fabricating photonic bandgap structures including Fabry-Perot resonators and optical filters for use at wavelengths in the range of about 0. 2-20. mu. m.

5919548, Jul 6, 1999

Aug 20, 1997

8/915071

Carole C. Barron - Albuquerque NM
Dale L. Hetherington - Albuquerque NM
Stephen Montague - Albuquerque NM

Sandia Corporation - Albuquerque NM

B32B 304

428138

A method is disclosed for micromachining recessed layers (e. g. sacrificial layers) of a microelectromechanical system (MEMS) device formed in a cavity etched into a semiconductor substrate. The method uses chemical-mechanical polishing (CMP) with a resilient polishing pad to locally planarize one or more of the recessed layers within the substrate cavity. Such local planarization using the method of the present invention is advantageous for improving the patterning of subsequently deposited layers, for eliminating mechanical interferences between functional elements (e. g. linkages) of the MEMS device, and for eliminating the formation of stringers. After the local planarization of one or more of the recessed layers, another CMP step can be provided for globally planarizing the semiconductor substrate to form a recessed MEMS device which can be integrated with electronic circuitry (e. g. CMOS, BiCMOS or bipolar circuitry) formed on the surface of the substrate.

5804084, Sep 8, 1998

Oct 11, 1996

8/729122

Robert D. Nasby - Albuquerque NM
Dale L. Hetherington - Albuquerque NM
Jeffry J. Sniegowski - Albuquerque NM
Paul J. McWhorter - Albuquerque NM
Christopher A. Apblett - Cedar Crest NM

Sandia Corporation - Albuquerque NM

H01L 2100

216 2

A process for removing topography effects during fabrication of micromachines. A sacrificial oxide layer is deposited over a level containing functional elements with etched valleys between the elements such that the sacrificial layer has sufficient thickness to fill the valleys and extend in thickness upwards to the extent that the lowest point on the upper surface of the oxide layer is at least as high as the top surface of the functional elements in the covered level. The sacrificial oxide layer is then polished down and planarized by chemical-mechanical polishing. Another layer of functional elements is then formed upon this new planarized surface.