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Daniel C WooSan Francisco, CA

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Daniel Woo Phones & Addresses

San Francisco, CA

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Career records & work history

Medicine Doctors

Daniel Woo

Specialties:
Neurology
Work:
University Of Cincinnati Physicians Neurology
222 Piedmont Ave STE 3200, Cincinnati, OH 45219
(513) 475-8730 (phone) (513) 475-8033 (fax)
Education:
Medical School
University of Cincinnati College of Medicine
Graduated: 1994
Procedures:
Lumbar Puncture, Sleep and EEG Testing
Conditions:
Dementia, Hemorrhagic stroke, Ischemic Stroke, Alzheimer's Disease, Bell's Palsy, Epilepsy, Infectious Diseases of the Brain or Spinal Cord, Insomnia, Intracranial Injury, Meningitis, Migraine Headache, Multiple Sclerosis (MS), Myasthenia Gravis (MG), Parkinson's Disease, Peripheral Nerve Disorders, Restless Leg Syndrome, Transient Cerebral Ischemia, Viral Meningitis
Languages:
English, Spanish
Description:
Dr. Woo graduated from the University of Cincinnati College of Medicine in 1994. He works in Cincinnati, OH and specializes in Neurology. Dr. Woo is affiliated with UC Medical Center.

Daniel H. Woo

Specialties:
Anesthesiology
Work:
Summit Anesthesia Associates PA
99 Beauvoir Ave FL 4, Summit, NJ 07901
(908) 598-1500 (phone) (908) 598-0197 (fax)
Site
Education:
Medical School
UMDNJ Robert Wood Johnson Medical School
Graduated: 1995
Languages:
English
Description:
Dr. Woo graduated from the UMDNJ Robert Wood Johnson Medical School in 1995. He works in Summit, NJ and specializes in Anesthesiology. Dr. Woo is affiliated with Overlook Medical Center.

License Records

Daniel Hyun Woo Han

Licenses:
License #: E054479 - Expired
Category: Emergency medical services
Issued Date: Jun 21, 2010
Expiration Date: Jun 30, 2012
Type: Los Angeles City FD

Publications & IP owners

Us Patents

Noise Suppression Using An Asymmetric Frequency-Locked Loop

US Patent:
8604852, Dec 10, 2013
Filed:
Sep 11, 2012
Appl. No.:
13/610469
Inventors:
Sebastian Turullols - Los Altos CA, US
Changku Hwang - Morgan Hill CA, US
Daniel Woo - San Francisco CA, US
Assignee:
Oracle International Corporation - Redwood Shores CA
International Classification:
H03L 7/06
US Classification:
327159, 327298, 327262
Abstract:
In an integrated circuit that provides a clock signal, an asymmetric frequency-locked loop (AFLL) includes a first digitally controlled oscillator (DCO) that outputs a first signal having a first fundamental frequency, and a second DCO that outputs a second signal having a second fundamental frequency that is less than the first fundamental frequency. Moreover, the AFLL includes control logic that selects one of the first DCO and the second DCO based on an instantaneous value of a power-supply voltage and an average power-supply voltage so that an impact of power-supply voltage variations on a time-critical path in the integrated circuit is reduced. For example, the control logic may select the first DCO if the instantaneous value of the power-supply voltage is greater than the average power-supply voltage; otherwise, the control logic may select the second DCO.

Afll With Increased Timing Margin

US Patent:
2015036, Dec 17, 2015
Filed:
Sep 26, 2014
Appl. No.:
14/498744
Inventors:
- Redwood City CA, US
Sebastian Turullols - Los Altos CA, US
Changku Hwang - Morgan Hill CA, US
Daniel S. Woo - San Francisco CA, US
International Classification:
H03L 7/08
H03L 7/099
Abstract:
In an integrated circuit that provides a clock signal, an asymmetric frequency-locked loop (AFLL) includes a first digitally controlled oscillator (DCO) that outputs a first signal having a first fundamental frequency, and a second DCO that outputs a second signal having a second fundamental frequency. The integrated circuit includes a voltage regulator that provides a power-supply voltage to the second DCO. Moreover, the AFLL includes control logic that selects one of the first DCO and the second DCO based on an instantaneous value of a power-supply voltage and an average power-supply voltage. Furthermore, the AFLL adjusts a gain of the selected DCO in the first sub-frequency-locked loop based on the instantaneous value of the power-supply voltage and the average power-supply voltage. In this way, an impact of power-supply voltage variations on a time-critical path in the integrated circuit is reduced.

Possible Relatives

Dennis L Woo  Douglas Y Woo  Eddie G Woo  Edmund F Woo  Eileen Woo  Ellen A Woo  Emily J Woo  Daniel M Standish  Daniel K Standridge  Daniel C Stanfield 

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