Danny C Vogel, Age 65Charlotte, NC

6483840, Nov 19, 2002

Jun 25, 2001

09/888866

Danny C. Vogel - Sudbury MA

LSI Logic Corporation - Milpitas CA

G06F 1300

370401, 370469, 709230, 710105

A circuit for converting data between communication protocols at different levels of a protocol stack. The circuit generally comprises a first processor and a second processor. The first processor may be configured to convert the data between a first communication protocol and a second communication protocol. The first processor may have a plurality of first rows each having at least one first block each configured to process a portion of the data. At least one of the first rows may have a plurality of the first blocks. The second processor may be configured to convert the data between the second communication protocol and a third communication protocol. The second processor may have a plurality of second rows each having at least one second block each configured to process a portion of the data. At least one of the second rows may have a plurality of the second blocks.

6839352, Jan 4, 2005

Dec 17, 1999

09/464267

Danny C. Vogel - Norfolk MA, US

LSI Logic Corporation - Milpitas CA

H04L 1228
H04J 316
H04J 324

3703951, 370466, 370474, 370907

A single-chip synchronous optical network (SONET) physical layer device includes first, second and third interface ports. An asynchronous transfer mode (ATM) interface circuit is coupled to the first interface port. A point-to-point protocol (PPP) processing circuit is coupled to the second interface port and the ATM interface circuit. A SONET framer circuit is coupled between the ATM interface circuit and the third interface port and between the PPP processing circuit and the third interface port. The device is programmable to allow multiple standard and non-standard data transmission modes, including transmitting ATM cells in SONET payloads, PPP frames in ATM cells in SONET payloads, PPP frames from a UTOPIA interface in SONET payloads and PPP frames directly in SONET payloads.

6912217, Jun 28, 2005

Jul 31, 2001

09/918736

Danny C. Vogel - Sudbury MA, US

LSI Logic Corporation - Milpitas CA

H04L012/28
H04J003/16
G06F013/28
G06F015/16

370389, 370465, 710 23, 709212

A system and method are presented for the encapsulation of a protocol stack in a voice telephony processor. Utilizing the system and method disclosed herein, digital voice telephony signals received in TDM frame-based format are converted to packet-based or cell-based format for transmission on a network, and vice-versa. The system and method may be embodied as a functional block within a specialized high-density integrated circuit voice processor. The voice processor employs on-chip digital signal processors (DSPs) to perform echo cancellation, dynamic range compression/expansion, and other processing on voice data. Advantageously, the encapsulation process of the disclosed herein does not impact the throughput of the DSPs. Instead, voice data is reformatted and prefixed with a header for the appropriate protocol layers using a dedicated on-chip packet control processor and linked list data structures managed by indexed direct memory access (DMA) controllers. Thus, data encapsulation has no impact on the signal processing activities.

6931027, Aug 16, 2005

Jul 25, 2000

09/624816

Danny Vogel - Sudbury MA, US
Bryan Robb - Cambridge MA, US
Clinton Seeman - Blackstone MA, US

LSI Logic Corporation - Milpitas CA

H04J003/18

370477, 370442, 370437

In a Framed Packet Bus (FPB) serial bus, an improved protocol and circuit layout for communication between devices grounded in the same chassis or chip. The improved protocol eliminates the requirement that bits have DC balance in their HIGH and LOW voltage levels. Consequently, bus overhead is reduced over prior techniques. In one example, data capacity utilization was increased from 80% to 95% and bus overhead was reduced from 20% to 5%. As a result of increased capacity, more packets of data may be carried across the serial bus, and any leftover bits within the frame cycle and in subsequent cycles may carry error detection information or be utilized as a control for the bus. In one preferred embodiment, the FPB serial bus configuration consists of sixteen serial lines arranged in parallel.

6959007, Oct 25, 2005

Jun 25, 2001

09/888902

Danny C. Vogel - Sudbury MA, US
Clinton P. Seeman - Blackstone MA, US

LSI Logic Corporation - Milpitas CA

H04L012/28
H04J003/16

370469, 370389, 710313, 713200

An apparatus comprising a media access controller (MAC), a configurable packet switch, and a network protocol stack in silicon. The network protocol stack may be configured to couple the media access controller to the configurable packet switch.

6983342, Jan 3, 2006

Oct 8, 2002

10/266232

Victor Helenic - Shrewsbury MA, US
Clinton P. Seeman - Blackstone MA, US
Danny C. Vogel - Sudbury MA, US

LSI Logic Corporation - Milpitas CA

G06F 13/14
H04Q 11/00

710305, 370366

An integrated circuit comprising a plurality of link layer controllers. The plurality of link layer controllers may be configured to operate independently in a first mode and cooperatively in a second mode.

6988251, Jan 17, 2006

Oct 14, 2003

10/684733

Danny C. Vogel - Sudbury MA, US

LSI Logic Corporation - Milpitas CA

G06F 17/50

716 2, 716 6, 716 11, 716 17

A semiconductor device comprising one or more diffused memories and one or more diffused regions. The one or more diffused regions may be configured to provide one or more ports for the one or more diffused memories.

7213224, May 1, 2007

Dec 2, 2003

10/725638

Danny Vogel - Sudbury MA, US
Carl Shaw - Boca Raton FL, US

LSI Logic Corporation - Milpitas CA

G06F 17/50

716 16, 716 17, 716 18

The present invention is directed to a customizable development and demonstration platform for structured ASICs. In an exemplary aspect of the present invention, the present platform may include a structured ASIC which is built on a slice and which may be flexible enough for a number of possible application developments. This flexibility may be achieved by incorporating a programmable processor in the structured ASIC and by defining interfaces and the use of an external FPGA in the present platform. The structured ASIC may include a complete ARM processor subsystem and a plurality of high speed SERDES ports. The processor subsystem may include a bus interface to the external FPGA, allowing custom gate development and test in the FPGA, prior to incorporating it into the customer product. Through the SERDES ports, the test block may be used to show the electrical characteristics of the SERDES IP. In addition, some SERDES ports may be driven from a link layer realized in the FPGA.