David H Auld, Age 404219 Sunnyside Ave N, Seattle, WA 98103

6353459, Mar 5, 2002

Mar 31, 1999

09/283823

Gerard K. Yeh - Redwood City CA
Hsiang O-Yang - Santa Clara CA
David Auld - San Jose CA

Teralogic, Inc. - Mountain View CA

H04N 701

348441, 348445

The invention provides a method and apparatus for conversion of video data from a source format to a second destination. Conversion can be performed in real time and intermediate data is stored in a buffer. Converted video data is written into the buffer at a first rate and read out of the buffer at a second rate. In order to avoid overflow and underflow conditions, a threshold value is determined based, at least in part, on the video format being converted. The threshold value indicates a point in frame conversion at which converted data is read out of the buffer.

6411333, Jun 25, 2002

Apr 2, 1999

09/285490

David Auld - San Jose CA
Gerard K. Yeh - Redwood City CA
Peter Trajmar - San Jose CA
C. Dardy Chang - Mountain View CA
Kevin P. Acken - Sunnyvale CA

Teralogic, Inc. - Mountain View CA

H04N 701

348441, 348445, 348448, 348458, 348581

The invention is a method and apparatus for processing image data stored in a memory. A read interface circuit is coupled to the memory to transfer a patch of the image data from the memory to a buffer. A scale filter is coupled to the read interface circuit to scale the image data in the patch from the buffer. A receive circuit is coupled to the scale filter to re-organize the scaled image data.

6411334, Jun 25, 2002

Mar 5, 1999

09/264140

Gerard K. Yeh - Redwood City CA
Anoush Khazeni - Sunnyvale CA
David Auld - San Jose CA
Bruce K. Holmer - Belmont CA

Teralogic, Inc. - Mountain View CA

H04N 1120

348445, 348581

The present invention is a method and apparatus for correcting aspect ratio of a display by scaling a source array of pixel data in a memory by a scale factor to a destination array of pixel data. The apparatus comprises a coefficient unit, a register unit, and an arithmetic unit. The coefficient unit is coupled to a buffer to load N coefficients. The register unit is coupled to the source array to load N pixel data synchronously with the coefficient unit. The N pixel data are started at a location in the source array according to the scale factor. The arithmetic unit is coupled to the coefficient unit and the register unit to perform a filtering operation on the loaded N pixel data using the corresponding N coefficients. The arithmetic unit generates a filtered output corresponding to a scaled pixel in the destination array.

6466220, Oct 15, 2002

Mar 5, 1999

09/263161

Joseph F. Cesana - Palo Alto CA
Peter Trajmar - San Jose CA
Edward Wang - San Jose CA
Hank Guo - Cupertino CA
Steve Chiou - Saratoga CA
Bruce K. Holmer - Belmont CA
David Auld - San Jose CA

Teralogic, Inc. - Mountain View CA

G06F 1300

345537, 345548, 345603

A method and apparatus for display of graphical data is described. The invention provides an architecture for graphics processing. The architecture includes pipelined processing and support for multi-regional graphics. In one embodiment, a graphics driver according to the invention can receive multiple independent streams of graphical data that can be in different graphical formats. The independent streams are synchronized and converted to a common format prior to being processed. In one embodiment, multi-regional graphics are supported with off-screen and on-screen memory regions for processing. The regions of the multi-regional graphic are rendered in an off-screen memory. The data in the off-screen memory are converted to a common format and copied to on-screen memory. The data in the on-screen memory is used to generate an output image. Alpha blending can also be programmed to provide multi-regional graphics or other graphical features.

6526583, Feb 25, 2003

Mar 5, 1999

09/263454

David R. Auld - San Jose CA
Bruce K. Holmer - Belmont CA
Gerard K. Yeh - Redwood City CA

Teralogic, Inc. - Mountain View CA

H04N 7173

725139, 725131, 725151, 348513, 348518, 348547, 709211, 711151, 712 31, 345418

According to one embodiment, a graphics/video processor includes a memory controller. The memory controller includes a first arbiter that receives memory client requests to access a memory device, and a first memory buffer coupled to the first arbiter. The first arbiter stores client requests that are selected by the first arbiter. The memory controller also includes a second arbiter coupled to the first memory buffer and a second memory buffer coupled to the second arbiter. The second arbiter receives requests from the memory client requests stored in the first memory buffer. The second memory buffer stores the client requests selected by the second arbiter. Further, the memory controller includes a third arbiter coupled to the second memory buffer. The third arbiter provides access of the memory device to the client requests stored in the second memory buffer.

6556193, Apr 29, 2003

Apr 2, 1999

09/285486

David Auld - San Jose CA
Gerard K. Yeh - Redwood City CA
Peter Trajmar - San Jose CA

Teralogic, Inc. - Mountain View CA

G06T 100

345418, 348452, 382261

The present invention is a method and apparatus for de-interlacing image data in a memory. A read interface circuit is coupled to the memory to transfer a patch of the image data from the memory to a buffer. A de-interlacing circuit is coupled to the read interface circuit to de-interlace the image data in the patch from the buffer. A receive circuit is coupled to the de-interlacing circuit to re-organize the de-interlaced image data.

7307667, Dec 11, 2007

Jun 28, 2004

10/880201

Gerard Yeh - Redwood City CA, US
David Auld - San Jose CA, US
Jackson F. Lee - Palo Alto CA, US
Joseph Cesana - Palo Alto CA, US
Hsiang O-Yang - Santa Clara CA, US
Xianliang Zha - Folsom CA, US
Zeljko Markovic - San Francisco CA, US

Zoran Corporation - Sunnyvale CA

H04N 5/46
H04N 5/907

348555, 348554, 348715, 348714, 348567, 345542, 345541

A method and an apparatus for an integrated high definition television controller are described. The integrated high definition digital television controller includes two or more the following functions in a single chip: MPEG2 Transport, Audio and Video Decoders, Video input capture and converter, flexible video scan rate converter, de-interlace processor, display controller and video D/A converters, graphics controller, a unified local bus, N-plane alpha blending, a warping engine, audio digital signal processor, disk drive interface, peripheral bus interfaces, such as PCI bus and local bus interfaces, various I/O peripherals, a bus bridge with a partitioned chip, and a CPU with caches. The integrated controller, in one embodiment, is designed to handle multiple television standards (for example ATSC, ARIB, DVB, AES, SMPTE, ITU) and designed to be deployed in various countries in the world.

7372873, May 13, 2008

Jun 27, 2003

10/608310

Nishit Kumar - San Jose CA, US
Timothy J. Vogt - Sunnyvale CA, US
David R. Auld - San Jose CA, US

Zoran Corporation - Sunnyvale CA

H04J 1/00
H04J 3/06
H04N 5/95

370484, 370486, 370509, 386 88

A method and a system for reconstructing a partial transport stream are described. One embodiment of the method includes time-stamping each packet when the packet arrives, storing of the selected subset of packets and the associated timestamps in a storage medium, reading the stored packets and their timestamps from the storage medium, and reconstructing the partial transport stream with the packets and their timestamps.