David A Beauchaine, Age 652018 159Th St, Vancouver, WA 98684

David Beauchaine Phones & Addresses

2018 159Th St, Vancouver, WA 98684 (360) 254-9240

2018 159Th Ave, Vancouver, WA 98684 (360) 254-9240

Westfield, NJ

Social networks

David A Beauchaine

Linkedin

Work

Company: Toyo tanso usa inc Dec 2011 to Apr 2016 Position: Senior manufacturing engineer

Education

Degree: Master of Science, Masters School / High School: Washington State University 1986 to 1988 Specialities: Materials Science, Engineering

Skills

Silicon • Silicon Carbide • Lpcvd • Aviation • Flight Training • Semiconductor Process Technology • Crystal Growth • Semiconductors • Characterization • Yield • Process Simulation • Solar Cells • Materials • Manufacturing • Semiconductor Industry

Industries

Semiconductors

Mentions for David A Beauchaine

Career records & work history

License Records

David Alan Beauchaine

Address:
2018 NE 159 Ave, Vancouver, WA 98684
Licenses:
License #: A0114919
Category: Airmen

David Beauchaine resumes & CV records

Resumes

David Beauchaine Photo 16

Flight Crew

Location:
Vancouver, WA
Industry:
Semiconductors
Work:
Toyo Tanso Usa Inc Dec 2011 - Apr 2016
Senior Manufacturing Engineer
Rec Wafer Norway As Apr 2010 - Dec 2011
Senior Technologist, Crystallization
Aeroflight Executive Services Apr 2008 - Apr 2010
C402 Captain
Seh America Feb 1983 - Jul 2007
Senior Engineer
Skywest Airlines Feb 1983 - Jul 2007
Flight Crew
Education:
Washington State University 1986 - 1988
Master of Science, Masters, Materials Science, Engineering
University of Washington
Bachelors, Bachelor of Science, Materials Science, Engineering
Skills:
Silicon, Silicon Carbide, Lpcvd, Aviation, Flight Training, Semiconductor Process Technology, Crystal Growth, Semiconductors, Characterization, Yield, Process Simulation, Solar Cells, Materials, Manufacturing, Semiconductor Industry

Publications & IP owners

Us Patents

Double Side Polished Wafers Having External Gettering Sites, And Method Of Producing Same

US Patent:
2003022, Dec 4, 2003
Filed:
Apr 9, 2003
Appl. No.:
10/410792
Inventors:
David Beauchaine - Vancouver WA, US
Timothy Brown - Vancouver WA, US
Sergei Koveshnikov - Vancouver WA, US
Romony San - Vancouver WA, US
International Classification:
B32B009/04
H01L029/30
US Classification:
428/064100, 428/446000
Abstract:
A semiconductor wafer manufacturing process is disclosed wherein a double side polished wafer having oxygen induced stacking faults to provide extrinsic gettering on the back surface of the wafer. The process includes polishing the back surface of the wafer, and depositing a thin polysilicon film on the polished back surface. The wafer is then subjected to a thermal oxidation step, wherein the polysilicon film is consumed by the thermal oxidation step. The oxide layer is then stripped from the back surface, leaving oxygen induced stacking faults on the back surface of the wafer. The front surface of the wafer is then polished, thereby producing a double side polished wafer containing extrinsic gettering sites on the polished back surface.

Double Side Polished Wafers Having External Gettering Sites, And Method Of Producing Same

US Patent:
2003022, Dec 4, 2003
Filed:
Apr 9, 2003
Appl. No.:
10/410790
Inventors:
David Beauchaine - Vancouver WA, US
Timothy Brown - Vancouver WA, US
Sergei Koveshnikov - Vancouver WA, US
Romony San - Vancouver WA, US
International Classification:
H01L021/302
H01L021/461
US Classification:
438/690000
Abstract:
A semiconductor wafer manufacturing process is disclosed wherein a double side polished wafer having oxygen induced stacking faults to provide extrinsic gettering on the back surface of the wafer. The process includes polishing the back surface of the wafer, and depositing a thin polysilicon film on the polished back surface. The wafer is then subjected to a thermal oxidation step, wherein the polysilicon film is consumed by the thermal oxidation step. The oxide layer is then stripped from the back surface, leaving oxygen induced stacking faults on the back surface of the wafer. The front surface of the wafer is then polished, thereby producing a double side polished wafer containing extrinsic gettering sites on the polished back surface.

Quartz To Quartz Seal Using Expanded Ptfe Gasket Material

US Patent:
2004006, Apr 1, 2004
Filed:
Oct 1, 2002
Appl. No.:
10/260268
Inventors:
David Beauchaine - Vancouver WA, US
Aaron Newton - Vancouver WA, US
Mike Tabor - Vancouver WA, US
Assignee:
SEH AMERICA INC. - Vancouver WA
International Classification:
C23C016/00
US Classification:
118/724000
Abstract:
A gasket material made from expanded PTFE for sealing high purity semiconductor furnace operations is provided. The gasket may be used in place of O-rings made of fluoro-rubber or standard PTFE material. Gaskets made of expanded PTFE provide greater flexibility and thus gives a better seal than standard O-rings.

Gettering Filter And Associated Method For Removing Oxygen From A Gas

US Patent:
2005005, Mar 10, 2005
Filed:
Sep 8, 2003
Appl. No.:
10/657606
Inventors:
David Beauchaine - Vancouver WA, US
Oleg Kononchuk - Brush Prairie WA, US
Assignee:
SEH America, Inc. - Vancouver WA
International Classification:
C01B013/00
H01L021/311
US Classification:
423219000, 438694000
Abstract:
A method and apparatus are provided for removing oxygen and moisture from a gas such that wafers subsequently exposed to the gas develop less haze. The apparatus includes a process chamber for receiving a wafer. The apparatus also includes a gettering filter in fluid communication with the process chamber for removing oxygen from a gas that passes through the gettering filter in route to the process chamber. The gettering filter includes a vessel and a plurality of pieces of an oxidizable material disposed within the vessel. The oxidizable material is selected to oxidize upon exposure to oxygen in the gas such that the gas exiting the vessel has less oxygen than the gas entering the vessel. The oxidizable material may also be selected such that the resulting oxide layer is etchable upon exposure to an etchant, thereby permitting the gettering filter to be regenerated.

Support Fixture For Semiconductor Wafers And Associated Fabrication Method

US Patent:
2005022, Oct 20, 2005
Filed:
Apr 16, 2004
Appl. No.:
10/826730
Inventors:
David Beauchaine - Vancouver WA, US
Aaron Newton - Vancouver WA, US
Assignee:
SEH America, Inc. - Vancouver WA
International Classification:
C23C016/00
US Classification:
118728000, 427249100
Abstract:
A support fixture is provided that includes a boat, a first layer deposited on at least a portion of the boat that has fewer impurities than the boat, and a second layer deposited on at least a portion of the first layer that is formed of a material having one or both of a hardness and a coefficient of thermal expansion that more closely matches the material properties of the wafers to be carried by the support fixture than does those of the boat and the first layer. For example, the boat and the first layer may be formed of silicon carbide and the second layer may be formed of polysilicon. A method of fabricating a support fixture having a boat coated with first and second layers, such as by sequential chemical vapor deposition steps, is also provided.

Double Side Polished Wafers Having External Gettering Sites, And Method Of Producing Same

US Patent:
6576501, Jun 10, 2003
Filed:
May 31, 2002
Appl. No.:
10/160146
Inventors:
David A. Beauchaine - Vancouver WA
Timothy L. Brown - Vancouver WA
Sergei V. Koveshnikov - Vancouver WA
Romony San - Vancouver WA
Assignee:
SEH America, Inc. - Vancouver WA
International Classification:
H01L 21335
US Classification:
438143, 438476
Abstract:
A semiconductor wafer manufacturing process is disclosed wherein a double side polished wafer having oxygen induced stacking faults to provide extrinsic gettering on the back surface of the wafer. The process includes polishing the back surface of the wafer, and depositing a thin polysilicon film on the polished back surface. The wafer is then subjected to a thermal oxidation step, wherein the polysilicon film is consumed by the thermal oxidation step. The oxide layer is then stripped from the back surface, leaving oxygen induced stacking faults on the back surface of the wafer. The front surface of the wafer is then polished, thereby producing a double side polished wafer containing extrinsic gettering sites on the polished back surface.

NOTICE: You may not use PeopleBackgroundCheck or the information it provides to make decisions about employment, credit, housing or any other purpose that would require Fair Credit Reporting Act (FCRA) compliance. PeopleBackgroundCheck is not a Consumer Reporting Agency (CRA) as defined by the FCRA and does not provide consumer reports.