David B Fite, Age 6474 Belknap Point Rd, Laconia, NH 03249

2003005, Mar 27, 2003

Aug 29, 2002

10/230758

Ronald Salett - Framingham MA, US
Nicholas Ilyadis - Pepperell MA, US
David Fite - Northborough MA, US

H04L012/28
H04L012/56

370/389000

A method and apparatus for providing data communication between stations on a network which optimizes the amount of resources required for a network switch. A first data frame is encoded with a source station identifier for the first station and a source switch identifier for the first switch. The first data frame is sent from the first switch to the second switch. A station list in the second switch is updated to indicate that the first station is associated with the first switch. Subsequent data frames having the same destination as the first switch are sent directly to the second switch. Any switch on the network need only identify the local ports attached to the switch, plus the number of switches on the network. The task of identifying all of the ports on the network is distributed across all switches on the network.

5619662, Apr 8, 1997

Aug 12, 1994

8/289613

Simon C. Steely - Hudson NH
David J. Sager - Acton MA
David B. Fite - Northborough MA

Digital Equipment Corporation - Maynard MA

G06F 930

395392

A pipelined processor includes an instruction box including a register mapper, to map register operand fields of a set of instructions and an instruction scheduler, fed by the set of instructions, to reorder the issuance of the set of instructions from the instruction processor. The mapped register operand fields are associated with the corresponding instructions of the reordered set of instructions prior to issuance of the instructions. The processor further includes a branch prediction table which maps a stored pattern of past histories associated with a branch instruction to a more likely prediction direction of the branch instruction. The processor further includes a memory reference tagging store associated with the instruction scheduler so that the scheduler can reorder memory reference instructions without knowing the actual memory location addressed by the memory reference instruction.

4888679, Dec 19, 1989

Jan 11, 1988

7/142794

Tryggve Fossum - Northboro MA
Ricky C. Hetherington - Northboro MA
David B. Fite - Northboro MA
Dwight P. Manley - Holliston MA
Francis X. McKeen - Westboro MA
John E. Murray - Acton MA

Digital Equipment Corporation - Maynard MA

G06F 938
G06F 15347

364200

A main memory and cache suitable for scalar processing are used in connection with a vector processor by issuing prefetch requests in response to the recognition of a vector load instruction. A respective prefetch request is issued for each block containing an element of the vector to be loaded from memory. In response to a prefetch request, the cache is checked for a "miss" and if the cache does not include the required block, a refill request is sent to the main memory. The main memory is configured into a plurality of banks and has a capability of processing multiple references. Therefore the different banks can be referenced simultaneously to prefetch multiple blocks of vector data. Preferably a cache bypass is provided to transmit data directly to the vector processor as the data from the main memory are being stored in the cache. In a preferred embodiment, a vector processor is added to a digital computing system including a scalar processor, a virtual address translation buffer, a main memory and a cache.

4985825, Jan 15, 1991

Feb 3, 1989

7/306866

David A. Webb - Berlin MA
David B. Fite - Northboro MA
Ricky C. Hetherington - Northboro MA
Francis X. McKeen - Westboro MA
Mark A. Firstenberg - Maynard MA
John E. Murray - Acton MA
Dwight P. Manley - Holliston MA
Ronald M. Salett - Framingham MA
Tryggve Fossum - Northboro MA

Digital Equipment Corporation - Maynard MA

G06F 938
G06F 1130
G06F 1210

364200

A technique for processing memory access exceptions along with pre-fetched instructions in a pipelined instruction processing computer system is based upon the concept of pipelining exception information along with other parts of the instruction being executed. In response to the detection of access exceptions at a pipeline stage, corresponding fault information is generated and transferred along the pipeline. The fault information is acted upon only when the instruction reaches the execution stage of the pipeline. Each stage of the instruction pipeline is ported into the front end of a memory unit adapted to perform the virtual-to-physical address translation; each port being provided with storage for virtual addresses accompanying an instruction as well as storage for corresponding fault information. When a memory access exception is encountered at the front end of the memory unit, the fault information generated therefrom is loaded into the storage and the port is prevented from accepting further references.

5167026, Nov 24, 1992

Feb 3, 1989

7/306833

John E. Murray - Acton MA
David B. Fite - Northboro MA
Mark A. Firstenberg - Maynard MA
Lawrence O. Herman - Hudson MA
Ronald M. Salett - Framingham MA

Digital Equipment Corporation - Maynard MA

G06F 930
G06F 938

395375

In a pipeline processor, simultaneous decoding of multiple specifiers in a variable-length instruction causes a peculiar problem of an intra-instruction read conflict that occurs whenever an instruction includes an autoincrement or an autodecrement specifier which references either directly or indirectly a register specified by a previously occurring specifier for the current instruction. To avoid stalls during the preprocessing of instructions by the instruction unit, register pointers rather than register data are usually passed to the excellent unit because register data is not always available at the time of instruction decoding. If an intra-instruction read conflict exists, however, the operand value specified by the conflicting register specifier is the initial value of the register being incremented or decremented, and this initial value will have been changed by the time that the execution unit executes the instruction. Preferably, the proper initial value is obtained prior to the incrementing or decrementing of the conflicting register by putting the instruction decoder into a special IRC mode in which only one specifier is decoded per cycle, and if a specifier being decoded is a register specifier, the content of the specified register is transmitted to the execution unit. Circuitry for detecting an intra-instruction read conflict is disclosed as well as an efficient method for handling interrupts, exceptions and flushes that may occur during the processing of an instruction having an intra-instruction read conflict.

5519841, May 21, 1996

Nov 12, 1992

7/974776

David J. Sager - Acton MA
Simon C. Steely - Hudson NH
David B. Fite - Northborough MA

Digital Equipment Corporation - Maynard MA

G06F 934

395412

A pipelined processor includes an instruction unit including a register mapper, to map register operand fields of a set of instructions and an instruction scheduler, fed by the set of instructions, to reorder the issuance of the set of instructions from the processor. The mapped register operand fields are associated with the corresponding instructions of the reordered set of instructions prior to issuance of the instructions. The processor further includes a branch prediction table which maps a stored pattern of past histories associated with a branch instruction to a more likely prediction direction of the branch instruction. The processor further includes a memory reference tagging store associated with the instruction scheduler so that the scheduler can reorder memory reference instructions without knowing the actual memory location addressed by the memory reference instruction.

5349651, Sep 20, 1994

Aug 9, 1991

7/746007

Ricky C. Hetherington - Northboro MA
David A. Webb - Berlin MA
David B. Fite - Northboro MA
John E. Murray - Acton MA
Tryggve Fossum - Northboro MA
Dwight P. Manley - Holliston MA

Digital Equipment Corporation - Maynard MA

G06F 1210
G06F 1200

395400

In the field of high speed computers it is common for a central processing unit to reference memory locations via a virtual addressing scheme, rather than by the actual physical memory addresses. In a multi-tasking environment, this virtual addressing scheme reduces the possibility of different programs accessing the same physical memory location. Thus, to maintain computer processing speed, a high speed translation buffer cache is employed to perform the necessary virtual-to-physical conversions for memory reference instructions. The translation buffer cache stores a number of previously translated virtual addresses and their corresponding physical addresses. A memory management processor is employed to update the translation buffer cache with the most recently accessed physical memory locations. The memory management processor consists of a state machine controlling hardware specifically designed for the purpose of updating the translation buffer cache. The memory management processor calculates an address of a location in the memory where the physical address is stored concurrently with the translation buffer cache comparing the virtual address with already stored virtual addresses.

5109495, Apr 28, 1992

Feb 3, 1989

7/306843

David B. Fite - Northboro MA
Tryggve Fossum - Northboro MA
William R. Grundmann - Hudson MA
Dwight P. Manely - Holliston MA
Francis X. McKeen - Westboro MA
John E. Murray - Acton MA
Ronald M. Salett - Framingham MA
Eileen Samberg - Southborough MA
Daniel P. Stirling - Shrewsbury MA

Digital Equipment Corp. - Maynard MA

G06F 934
G06F 938

395375

To execute variable-length instructions independently of instruction preprocessing, a central processing unit is provided with a set of queues in the data and control paths between an instruction unit and an execution unit. The queues include a "fork" queue, a source queue, a destination queue, and a program counter queue. The fork queue contains an entry of control information for each instruction processed by the instruction unit. This control information corresponds to the opcode for the instruction, and preferably it is a microcode "fork" address at which a microcode execution unit begins execution to execute the instruction. The source queue specifies the source operands for the instruction. Preferably the source queue stores source pointers and the operands themselves are included in a separate "source list" in the case of operands fetched from memory or immediate data from the instruction stream, or are the contents of a set of general purpose registers in the execution unit. The destination queue specifies the destination for the instruction, for example, either memory or general purpose registers.