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David Sek Fong, Age 78163 N Main St #2, Milpitas, CA 95035

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Known as:
David S Fong David Fui Fong David F Fong David Sek I
Related to:
Alicia Fong 84

David Fong Phones & Addresses

163 N Main St #2, Milpitas, CA 95035 (408) 263-8523

4096 Grama Ter, Fremont, CA 94536

1367 Mayfair Ave, Daly City, CA 94015

Bowling Green, OH

Cadiz, CA

Mentions for David Sek Fong

Career records & work history

Medicine Doctors

David Fong Photo 1

Dr. David M Fong, Oakland CA - DDS (Doctor of Dental Surgery)

Specialties:
Dentistry
Address:
1730 Franklin St Suite 302, Oakland, CA 94612
(510) 452-1156 (Phone) (510) 452-1013 (Fax)
Languages:
English
David Fong Photo 2

David Fong, Oakland CA - DPM (Doctor of Podiatric Medicine)

Specialties:
Podiatry
Address:
David Fong DPM
357 15Th St, Oakland, CA 94612
(510) 268-1921 (Phone)
Languages:
English
Hospitals:
David Fong DPM
357 15Th St, Oakland, CA 94612
Chinese Hospital
845 Jackson Street, San Francisco, CA 94133

David W. Fong

Specialties:
Obstetrics & Gynecology
Work:
David W.I. Fong MD
2840 Legacy Dr STE 300, Frisco, TX 75034
(972) 890-9250 (phone) (214) 872-4937 (fax)
Education:
Medical School
University of Southern California Keck School of Medicine
Graduated: 1995
Languages:
English, Spanish
Description:
Dr. Fong graduated from the University of Southern California Keck School of Medicine in 1995. He works in Frisco, TX and specializes in Obstetrics & Gynecology. Dr. Fong is affiliated with Baylor Medical Center At Frisco, Medical Center Of Plano and Texas Health Presbyterian Hospital.
David Fong Photo 3

David M Fong, Oakland CA

Specialties:
Dentist
Address:
1730 Franklin St, Oakland, CA 94612
David Fong Photo 4

David Fong, Oakland CA

Specialties:
Podiatrist
Address:
357 15Th St, Oakland, CA 94612
950 Stockton St, San Francisco, CA 94108

David Fong resumes & CV records

Resumes

David Fong Photo 42

David Fong - San Francisco, CA

Work:
IT. Specialists, Public Health Institute Jun 2010 to 2000 Best Buy - San Francisco, CA Apr 2007 to May 2010
Computer Sales Associate
Education:
Public Health Institute - Oakland, CA Jun 2010 to 2000
design Comptia A+/ City College of San Francisco Aug 2012 Heald College - San Francisco, CA Apr 2002
Associate of Science in Computer Technology

Publications & IP owners

Us Patents

High D.c. Voltage To Low D.c. Voltage Circuit Converter

US Patent:
6670845, Dec 30, 2003
Filed:
Jul 16, 2002
Appl. No.:
10/197281
Inventors:
David Fong - Cupertino CA
Assignee:
Silicon Storage Technology, Inc. - Sunnyvale CA
International Classification:
G05F 324
US Classification:
327541, 327543, 323313
Abstract:
A high DC voltage to low DC voltage circuit has a first NMOS transistor with the first terminal connected to the source of the high DC voltage and the second terminal connected to supply the low DC voltage. The gate is connected to a middle node of a resistor divider circuit having one end connected to the source of the high DC voltage and the other end to a common node. A plurality of serially connected NMOS transistors has a first end connected to the common node and a second end connected to ground. Each of the NMOS transistors in the plurality of serially connected NMOS transistors has its gate connected to its first terminal and to the second terminal of the immediate adjacent NMOS transistor.

Programming Methods And Circuits For Semiconductor Memory Cell And Memory Array Using A Breakdown Phenomena In An Ultra-Thin Dielectric

US Patent:
6671040, Dec 30, 2003
Filed:
Sep 26, 2002
Appl. No.:
10/256483
Inventors:
David Fong - Cupertino CA
Fei Ye - Cupertino CA
Jack Zezhong Peng - San Jose CA
Assignee:
Kilopass Technologies, Inc. - Sunnyvale CA
International Classification:
G11C 1604
US Classification:
35618908, 36518909, 36518911
Abstract:
A programming circuit includes a wordline decoder, an adjustable voltage generator, and a column transistor. The programming circuit is useful in programming a memory cell comprised of a select transistor and a data storage element. The data storage element is programmed by a programming current. The amount of the programming current can be modulated by the column transistor, the select transistor, or the adjustable voltage generator.

High Density Semiconductor Memory Cell And Memory Array Using A Single Transistor

US Patent:
6777757, Aug 17, 2004
Filed:
Apr 26, 2002
Appl. No.:
10/133704
Inventors:
Jack Zezhong Peng - San Jose CA
David Fong - Cupertino CA
Assignee:
Kilopass Technologies, Inc. - Sunnyvale CA
International Classification:
H01L 2994
US Classification:
257368, 257390, 257E2708, 257 5, 365177, 365178
Abstract:
A programmable memory cell comprised of a transistor located at the crosspoint of a column bitline and a row wordline is disclosed. The transistor has its gate formed from the column bitline and its source connected to the row wordline. The memory cell is programmed by applying a voltage potential between the column bitline and the row wordline to produce a programmed n+ region in the substrate underlying the gate of the transistor.

Method Of Testing The Thin Oxide Of A Semiconductor Memory Cell That Uses Breakdown Voltage

US Patent:
6791891, Sep 14, 2004
Filed:
Apr 2, 2003
Appl. No.:
10/406406
Inventors:
Jack Zezhong Peng - San Jose CA
Harry Shengwen Luan - Saratoga CA
Jianguo Wang - Cupertino CA
Zhongshan Liu - Plano TX
David Fong - Cupertino CA
Fei Ye - Cupertino CA
Assignee:
Kilopass Technologies, Inc. - Sunnyvale CA
International Classification:
G11C 700
US Classification:
365201, 365149
Abstract:
A method of testing a memory cell is disclosed. The memory cell has a data storage element constructed around an ultra-thin dielectric, such as a gate oxide, which is used to store information by stressing the ultra-thin dielectric into breakdown (soft or hard breakdown) to set the leakage current level of the memory cell. In order to ensure that the gate oxide underlying the data storage elements are of sufficient quality for programming, the memory cells of a memory array may be tested by applying a voltage across the gate oxide of the data storage element and measuring the current flow. Resultant current flow outside of a predetermined range indicates a defective memory cell.

High Density Semiconductor Memory Cell And Memory Array Using A Single Transistor

US Patent:
6856540, Feb 15, 2005
Filed:
May 30, 2003
Appl. No.:
10/448505
Inventors:
Jack Zezhong Peng - San Jose CA, US
David Fong - Cupertino CA, US
Assignee:
Kilopass Technologies, Inc. - Sunnyvale CA
International Classification:
G11C011/34
US Classification:
365177, 36518514, 36518528
Abstract:
A programmable memory cell comprised of a transistor located at the crosspoint of a column bitline and a row wordline is disclosed. The transistor has its gate formed from the column bitline and its source connected to the row wordline. The memory cell is programmed by applying a voltage potential between the column bitline and the row wordline to produce a programmed n+region in the substrate underlying the gate of the transistor.

Methods And Circuits For Testing Programmability Of A Semiconductor Memory Cell And Memory Array Using A Breakdown Phenomenon In An Ultra-Thin Dielectric

US Patent:
7031209, Apr 18, 2006
Filed:
Mar 9, 2004
Appl. No.:
10/796270
Inventors:
Jianguo Wang - Cupertino CA, US
David Fong - Cupertino CA, US
Jack Zezhong Peng - San Jose CA, US
Fei Ye - Cupertino CA, US
Michael David Fliesler - Santa Cruz CA, US
Assignee:
Kilopass Technology, Inc. - Sunnyvale CA
International Classification:
G11C 7/00
US Classification:
365201, 36518909, 36523006
Abstract:
A method of testing the programmability of a memory cell is disclosed. The memory cell comprises a select transistor and a data storage element. The method comprises applying a test voltage across the data storage element. The select transistor is turned on. Finally, a current flow through the data storage element when the test voltage is applied is measured. A test positive signal is indicated if the current flow is greater than a reference.

Methods And Circuits For Programming Of A Semiconductor Memory Cell And Memory Array Using A Breakdown Phenomenon In An Ultra-Thin Dielectric

US Patent:
7042772, May 9, 2006
Filed:
Jun 2, 2004
Appl. No.:
10/859934
Inventors:
Jianguo Wang - Cupertino CA, US
David Fong - Cupertino CA, US
Jack Zezhong Peng - San Jose CA, US
Fei Ye - Cupertino CA, US
Michael David Fliesler - Santa Cruz CA, US
Assignee:
Kilopass Technology, Inc. - Sunnyvale CA
International Classification:
G11C 16/06
US Classification:
36518909, 36518523, 365196
Abstract:
A method of programming a memory cell is disclosed. The memory cell comprises a select transistor and a data storage element. The method comprises allowing current to flow through the data storage element until a predetermined current or voltage is detected. If the current or voltage exceeds a threshold, then the programming is deemed complete.

Combination Field Programmable Gate Array Allowing Dynamic Reprogrammability

US Patent:
7064973, Jun 20, 2006
Filed:
May 28, 2004
Appl. No.:
10/857667
Inventors:
Jack Zezhong Peng - San Jose CA, US
Zhongshang Liu - Plano TX, US
David Fong - Cupertino CA, US
Fei Ye - Cupertino CA, US
Assignee:
KLP International, Ltd. - Santa Clara CA
International Classification:
G11C 11/24
US Classification:
365149, 36518908, 327 44
Abstract:
A cell that can be used as a dynamic memory cell for storing data used in programming a field programmable gate array (FPGA) is disclosed. The cell comprises a select transistor having a gate, a source, and a drain, the gate connected to said write bitline, the source connected to a floating point node, and the drain connected to a row wordline. A sense device determines the data stored on the floating point node. Finally, switch that is controlled by the floating point node is provided.

Possible Relatives

Cynthia Fong  Daisy Fong  Deborah L Fong  Debra A Fong  Daniel Fong  Aaron B Fong  Danny K Fong  David Last  David W Johnson  David Stamps 

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