David C HartwellLady Lake, FL

6360285, Mar 19, 2002

Jun 30, 1994

08/269234

David M. Fenwick - Nashua NH
Denis Foley - Shrewsbury MA
David Hartwell - Bolton MA
Ricky C. Hetherington - Westboro MA
Dale R. Keck - Shrewsbury MA
Elbert Bloom - Marlboro MA

Compaq Computer Corporation - Houston TX

G06F 1202

710 17, 711 5

In accordance with the present invention, an apparatus includes a system bus having memory bank available signals. Coupled to the system bus are at least two memory modules, each having at least one memory bank. Each memory module includes a mechanism for associating each memory bank with one of the memory bank available signals. Further, each memory module includes logic for determining an availability status of each memory bank and for providing the associated memory bank busy signal with values reflecting the availability status of the memory bank. Additionally, at least two commander modules are coupled to the system bus and include logic, responsive to the memory bank available signals for preventing the commander module from gaining control of the system bus when the commander is attempting to access a memory bank determined to be unavailable. With such an arrangement, only commander modules seeking to access memory banks which are available will be allowed to gain control of the system bus. This avoids stalling the system bus and improves system performance by allowing all initiated transactions to complete as quickly as possible.

6629257, Sep 30, 2003

Aug 31, 2000

09/652980

David Hartwell - Bolton MA

Hewlett-Packard Development Company, L.P. - Houston TX

G06F 124

713502, 713500, 713501, 713503, 713600, 395284

An initialization/reset circuit automatically resets and initializes a clocking subsystem having a phase locked loop (PLL) within a data processing system. The logic circuit is contained within an input/output (I/O) interface of the system. Clock signals are provided from a clock source of the data processing system to the PLL. In addition to the PLL, the initialization/reset logic circuit comprises a counter, a first timer circuit and a second watchdog timer.

6640272, Oct 28, 2003

Aug 31, 2000

09/652494

David Hartwell - Bolton MA
David Golden - Woonsocket RI
Glenn Herdeg - Acton MA

Hewlett-Packard Development Company, L.P. - Houston TX

G06F 1300

710104, 710300, 710301, 710302, 710303, 710304

An automated backplane cable connection system (and method) for manually connecting a cluster of processor modules to other modules or I/O boxes uses a programmed server management control console which identifies connection terminals provided on the processors/I/O boxes and controls LEDs which are associated with the connection terminals, on a one to one basis. The programmed server management console uses diagnostic circuitry and causes LEDs corresponding to connection terminals engaged by a newly made cable connection to initially light up, and enables them to turn off if the newly made cable connection is proper as verified by the diagnostic circuitry. The cluster of processor modules may be connected to a plurality of I/O boxes through an Ethernet LAN. The processor modules or I/O boxes may have sufficient nonvolatile memory to remember backplane cable connections which have already been made according to user needs, as initially guided by the programmed server management control console. From the memory, replacement of cables when necessary, is facilitated, without the need for assistance by the server management console.

6701387, Mar 2, 2004

Aug 31, 2000

09/652644

Roger Pannel - Nashua NH
David W. Hartwell - Bolton MA
Samuel H. Duncan - Arlington MA
Rajen Ramchandani - Arlington MA
Andrej Kocev - Shirley MA
Jeffrey Willcox - Westford MA
Steven Ho - Westford MA

Hewlett-Packard Development Company, L.P. - Houston TX

G06F 1300

710 22, 710 23, 710 28, 710 33, 710 36, 710 39, 710 52, 710 53, 710 56, 710 60, 710107, 710308, 710310

A method and apparatus for accommodating the speed requirements of a DMA read request from PCI protocol I/O devices attached via a DMA to a multiprocessor system mesh. A bridge between the device controller and the mesh is described which buffers the data from the memory in cache lines from which the data is delivered finally to the I/O device. The system is adaptive in that the number of cache lines required in past reads are remembered and used to determine if the number of cache lines is reduced or increased.

6724850, Apr 20, 2004

Aug 31, 2000

09/652645

David Hartwell - Bolton MA

Hewlett-Packard Development Company, L.P. - Houston TX

G06F 1100

375376, 714 11, 395550

A phase-locked loop (PLL) circuit is used to synchronize data transfers between a fast clock and a slow clock domain. The data transfer can be deterministic, where the fast clocks are generated by a first PLL and the slow clocks are generated by a second PLL. The second PLL is used to create a phase relationship between the first PLL output clock and a third PLL output clock. The phase relationship can provide for a deterministic data transfer.

6738836, May 18, 2004

Aug 31, 2000

09/652391

Richard E. Kessler - Shrewsbury MA
Samuel H. Duncan - Arlington MA
David W. Hartwell - Bolton MA
David A. J. Webb, Jr. - Groton MA
Steve Lang - Stow MA

Hewlett-Packard Development Company, L.P. - Houston TX

G06F 1300

710 22, 710 23, 710 28, 710 33, 710 36, 710 37, 710 65, 710105, 710107, 712205

A system that supports a high performance, scalable, and efficient I/O port protocol to connect to I/O devices is disclosed. A distributed multiprocessing computer system contains a number of processors each coupled to an I/O bridge ASIC implementing the I/O port protocol. One or more I/O devices are coupled to the I/O bridge ASIC, each I/O device capable of accessing machine resources in the computer system by transmitting and receiving message packets. Machine resources in the computer system include data blocks, registers and interrupt queues. Each processor in the computer system is coupled to a memory module capable of storing data blocks shared between the processors. Coherence of the shared data blocks in this shared memory system is maintained using a directory based coherence protocol. Coherence of data blocks transferred during I/O device read and write accesses is maintained using the same coherence protocol as for the memory system. Data blocks transferred during an I/O device read or write access may be buffered in a cache by the I/O bridge ASIC only if the I/O bridge ASIC has exclusive copies of the data blocks.

6920516, Jul 19, 2005

Aug 31, 2001

09/944516

David W. Hartwell - Bolton MA, US
Samuel H. Duncan - Arlington MA, US
David T. Mayo - Boxboro MA, US
David J. Golden - Woonsocket RI, US

Hewlett-Packard Development Company, L.P. - Houston TX

G06F013/24

710263, 710262, 710266

An anti-starvation interrupt protocol for use in avoiding livelock in a multiprocessor computer system is provided. At least one processor is configured to include first and second control status registers (CSRs). The first CSR buffers information, such as interrupts, received by the processor, while the second CSR keeps track of the priority level of the interrupts. When an interrupt controller receives an interrupt, it issues a write transaction to the first CSR at the processor. If the first CSR has room to accept the write transaction, the processor returns an acknowledgement, whereas if the first CSR is already full, the processor returns a no acknowledgment. In response to a no acknowledgment, the interrupt controller increments an interrupt starvation counter, and checks to see whether the counter exceeds a threshold. If not, the interrupt controller waits a preset time and reposts the write transaction. If it does, the interrupt controller issues a write transaction having a higher priority to the second CSR.

6976184, Dec 13, 2005

Aug 27, 2003

10/649523

David Hartwell - Bolton MA, US

Hewlett-Packard Development Company, L.P. - Houston TX

G06F001/04

713500, 713375, 713400, 713501, 713502, 713503, 713600, 375371, 375373, 375376, 327156, 327160, 327162

A system and method for initializing and resetting a clocking subsystem having a phased locked loop (PLL) within an input/output interface of a data processing system. A first timer generates signals in response to receiving clock signals from a clock source. A second timer detects the presence or absence of signals from the first timer and in response to an absence outputs a circuit reset signal to a circuit. The circuit in turn issues a reset signal to the PLL and to other systems.