David J Lilja2392 Timber Ave, Saint Paul, MN 55119

8634233, Jan 21, 2014

May 18, 2012

13/475544

David J. Lilja - Maplewood MN, US
Jian-Ping Wang - Shoreview MN, US
Andrew P. Lyle - Boise ID, US
Shruti R. Patil - Santa Clara CA, US
Jonathan D. Harms - Hopkins MN, US
Xiaofeng Yao - San Jose CA, US

Regents of the University of Minnesota - Minneapolis MN

G11C 11/16

365158, 365148, 977935

Systems and methods that enable direct communications between magnetic tunnel junctions are provided. In one embodiment, a device includes multiple input magnetic tunnel junctions and an output magnetic tunnel junction. The multiple input magnetic tunnel junctions are connected in parallel, and the output magnetic tunnel junction is connected in series to the input magnetic tunnel junctions. In another embodiment, a device includes a first magnetic tunnel junction, a second magnetic tunnel junction, and a nano-magnetic channel. Each of the first and the second magnetic tunnel junctions has a free layer, a nonmagnetic layer, and a fixed layer. The nano-magnetic channel connects the free layer of the first magnetic tunnel junction to the free layer of the second magnetic tunnel junction.

2003000, Jan 2, 2003

Jul 2, 2001

09/897843

Nicolai Kosche - San Francisco CA, US
Chris Hescott - Minneapolis MN, US
Qing Zhao - Urbans IL, US
Youngsoo Choi - Pleasanton CA, US
David Lilja - Maplewood MN, US

G06F009/45

717/154000

A method of improving a prediction rate for instructions in code includes determining a sequence from profile information; and transforming the code based on the determined sequence. A method of improving processor performance includes transforming a set of branches into a second set of branches, wherein the second set of branches comprises the original set of branches; and a sequence of branches likely to execute as an entity. A processor includes means for processing instructions; and means for transforming a set of branches into a second set of branches, wherein the second set of branches comprises the original set of branches; and a sequence of branches likely to execute as an entity.

2003018, Sep 25, 2003

Mar 20, 2002

10/102084

Steven Kunkel - Rochester MN, US
David Lilja - Maplewood MN, US
Resit Sendag - Minneapolis MN, US

International Business Machines Corporation - Armonk NY

G06F009/00

712/225000, 712/235000

It has been determined that, in a superscalar computer processor, executing load instructions issued along an incorrectly predicted path of a conditional branch instruction eventually reduces the number of cache misses observed on the correct branch path. Executing these wrong-path loads provides an indirect prefetching effect. If the processor has a small L1 data cache, however, this prefetching pollutes the cache causing an overall slowdown in performance. By storing the execution results of mispredicted paths in memory, such as in a wrong path cache, the pollution is eliminated. A wrong path cache can improve processor performance up to 17% in simulations using a 32 KB data cache. A fully-associative eight-entry wrong path cache in parallel with a 4 KB direct-mapped data cache allows the execution of wrong path loads to produce an average processor speedup of 46%. The wrong path cache also results in 16% better speedup compared to the baseline processor equipped with a victim cache of the same size. Thus, the execution and storage of loads that are known to be from a mispredicted branch path significantly improves the performance of aggressive computer processor designs. This effect is even more important as the disparity between the processor cycle time and the memory speed continues to increase.

2008023, Oct 2, 2008

Mar 28, 2007

11/692731

Haowei Bai - Glendale AZ, US
David J. Lilja - Maplewood MN, US

HONEYWELL INTERNATIONAL, INC. - Morristown NJ

H04L 12/56

370230

Methods and apparatus are provided to improve data throughput in a wireless, wireline or a combination wireless and wireline communication system. A congestion control manager selects between an assumption based congestion control algorithm and a speculation based congestion control algorithm. The selected algorithm generates data recovery instructions including instructions for resizing, or not, congestion window sizing for the communication gateways. By making the selection between the assumption based congestion control algorithm and the speculation based congestion control algorithm based upon network information, data recovery and throughput is optimized for networks having lossy data links.

2008023, Oct 2, 2008

Mar 28, 2007

11/692758

Haowei Bai - Glendale AZ, US
David J. Lilja - Maplewood MN, US

HONEYWELL INTERNATIONAL, INC. - Morristown NJ

H04L 12/56

370231

Methods and apparatus are provided to reduce data congestion and thus improve data throughput in gateways used in a wireless, wireline or a combination wireless and wireline communication system. The congestion management system optimally resizes, or not, congestion window (or buffer) sizing and threshold for the communication gateways based upon mathematical models. Application of the inventive congestion management method optimizes data recovery and throughput in communication networks, particularly those networks having lossy data links.

2021037, Dec 2, 2021

May 27, 2021

17/332540

- Lafayette LA, US
S. Rasoul Faraji - Minneapolis MN, US
Kiarash Bazargan - Minneapolis MN, US
David Lilja - Minneapolis MN, US

University of Louisiana at Lafayette - Lafayette LA

G06N 3/04
G06F 9/30
G09G 3/20

Disclosed herein is a low-cost, high-performance, and energy-efficient near-sensor convolution engine based on pulsed unary processing. The disclosed engine removes the necessity of using costly analog-to-digital converters. Synthesis results show that the proposed pulse-based design significantly improves the hardware cost and energy consumption compared to the conventional fixed-point binary and also to the stochastic computing-based designs.

2020040, Dec 24, 2020

Jun 19, 2020

16/906122

- Minneapolis MN, US
David J. Lilja - Lake Elmo MN, US
Marcus Riedel - Shorewood MN, US
Kiarash Bazargan - Plymouth MN, US
Sayed Abdolrasoul Faraji - Minneapolis MN, US
Bingzhe Li - Falcon Heights MN, US

G06F 7/58
H03K 3/84

Example devices are described that include a computational unit configured to process first set of data bits encoding a first numerical value and a second set of data bits encoding a second numerical value. The computational unit includes a bit-stream generator configured to generate bit combinations representing first and second bit sequences that encode the first and second numerical values, respectively, based on a proportion of the data bits in the sequence that are high relative to the total data bits. The first bit sequence is generated using a first Sobol sequence source, and the second bit sequence is generated using a second Sobol sequence source different from the first Sobol sequence source. The device also includes computation logic configured to perform a computational operation on the bit combinations and produce an output bit-stream having a set of data bits indicating a result of the computational operation.

2020014, May 7, 2020

Nov 5, 2019

16/674488

- Minneapolis MN, US
David J. Lilja - Maplewood MN, US
Marcus Riedel - Shorewood MN, US
Kiarash Bazargan - Plymouth MN, US

G06N 3/063
H03M 1/50
G06F 7/24
G06F 7/20

Various implementations of sorting networks are described that utilize time-encoded data signals having encoded values. In some examples, an electrical circuit device includes a sorting network configured to receive a plurality of time-encoded signals. Each time-encoded signal of the plurality of time-encoded signals encodes a data value based on a duty cycle of the respective time-encoded signal or based on a proportion of data bits in the respective time-encoded signal that are high relative to the total data bits in the respective time-encoded signal. The sorting network is also configured to sort the plurality of time-encoded signals based on the encoded data values of the plurality of time-encoded signals.