David G Sanner, Age 75127 4Th St, Brooklyn, WI 53521

David Sanner Phones & Addresses

127 4Th St, Brooklyn, WI 53521

18308 Evansville Brooklyn Rd, Evansville, WI 53536

Rochester, MN

Work

Position: Farmer

Education

Degree: High school graduate or higher

Mentions for David G Sanner

Career records & work history

Lawyers & Attorneys

David Sanner Photo 1

David Sanner - Lawyer

Office:
Craig Realty Grp.
Specialties:
Litigation, Business, Commercial, Real Estate, Probate, Probate
ISLN:
904047576
Admitted:
1974
University:
University of California, B.A.
Law School:
University of California, J.D.

David Sanner resumes & CV records

Resumes

David Sanner Photo 36

David Sanner

David Sanner Photo 37

David Sanner

David Sanner Photo 38

David Sanner

David Sanner Photo 39

David Sanner

Publications & IP owners

Us Patents

Detecting A Deadlock Condition By Monitoring Firmware Inactivity During The System Ipl Process

US Patent:
8230429, Jul 24, 2012
Filed:
May 30, 2008
Appl. No.:
12/129893
Inventors:
Van Hoa Lee - Cedar Park TX, US
David Dean Sanner - Rochester MN, US
Alan Hlava - Mazeppa MN, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 9/46
G06F 9/44
US Classification:
718102, 717124, 717127
Abstract:
Illustrative embodiments manage deadlock in a data processing system during an IPL process that includes monitoring the usage of locks in the Hardware Object Model (HOM) of the data processing system. The process further includes detecting a deadlock condition in response to an indication of the IPL process in the data processing system entering a hung state when at least one lock is in use. The process also includes handling the deadlock condition by performing one or more of the following: recording error information for the deadlock condition, and terminating the IPL process.

Generate Diagnostic Data For Overdue Thread In A Data Processing System

US Patent:
8495430, Jul 23, 2013
Filed:
Mar 10, 2011
Appl. No.:
13/044640
Inventors:
Van H. Lee - Cedar Park TX, US
David D. Sanner - Rochester MN, US
Thi N. Tran - Round Rock TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 11/00
US Classification:
714 381
Abstract:
Disclosed is a computer implemented method, computer program product, and apparatus for generating diagnostic data for a thread. A service processor may begin by executing the computer usable program code to allocate a first thread to a monitoring function. The service processor determines if a second thread is running, wherein the second thread is associated with an operation. The service processor obtains an object pointer from a list of running threads, wherein the object pointer references a time data structure associated with the second thread, the time data structure comprising a maximum running time interval and a check time. The service processor calculates the check time as a maximum running time interval added to an initially sampled timestamp. The service processor determines if a current time exceeds the check time. In addition, the service processor generates an error log, responsive to a determination that the current time exceeds the check time.

Monitoring And Verifying A Clock State Of A Chip

US Patent:
8578219, Nov 5, 2013
Filed:
Mar 14, 2011
Appl. No.:
13/046865
Inventors:
Daniel M. Crowell - Rochester MN, US
David D. Sanner - Rochester MN, US
Thi N. Tran - Round Rock TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 11/00
US Classification:
714 55, 713500
Abstract:
A mechanism is provided for monitoring and verifying a clock state of a chip that does not write out clock state information. Responsive to identifying an access to the chip, the access is scanned to identify a chip register and a clock domain that will be accessed. A determination is made as to whether a bit of a clock trust unit associated with the chip register and the clock domain indicates whether to trust a clock state associated with the bit in a logical clock state unit. Responsive to the bit of the clock trust unit indicating that the clock state associated with the bit in the logical clock state unit is trusted, the clock state from the logical clock state unit is identified. Responsive to the clock state matching the clock state required by the access, the access is forwarded to the chip for execution.

Non-Disruptive Hardware Change

US Patent:
8650431, Feb 11, 2014
Filed:
Aug 24, 2010
Appl. No.:
12/862492
Inventors:
Michael S. Floyd - Cedar Park TX, US
Ryan J. Pennington - Austin TX, US
Harmony L. Prince - Austin TX, US
Kevin F. Reick - Round Rock TX, US
David D. Sanner - Rochester MN, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 11/00
US Classification:
714 3
Abstract:
A method, system, and computer program product for changing hardware in a data processing system without disrupting processes executing on the data processing system. A hardware change to a selected portion of hardware in the data processing system may be required, such as to repair hardware errors or to implement a system update. Responsive to a determination that a hardware change to the selected portion of the hardware is required, a process being performed by the selected portion is moved from the selected portion of the hardware to an alternate portion of the hardware. The hardware change is applied to the selected portion of the hardware. The selected portion of the hardware is returned for use by the data processing system after the hardware change is applied.

Generate Diagnostic Data For Overdue Thread In A Data Processing System

US Patent:
2010007, Mar 25, 2010
Filed:
Sep 22, 2008
Appl. No.:
12/235031
Inventors:
Van H. Lee - Cedar Park TX, US
David D. Sanner - Rochester MN, US
Thi N. Tran - Round Rock TX, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:
G06F 11/00
G06F 11/30
G06F 9/46
G06F 1/32
US Classification:
714 39, 718100, 713323, 718107, 718102
Abstract:
Disclosed is a computer implemented method, computer program product, and apparatus for generating diagnostic data for a thread. A service processor may begin by executing the computer usable program code to allocate a first thread to a monitoring function. The service processor determines if a second thread is running, wherein the second thread is associated with an operation. The service processor obtains an object pointer from a list of running threads, wherein the object pointer references a time data structure associated with the second thread, the time data structure comprising a maximum running time interval and a check time. The service processor calculates the check time as a maximum running time interval added to an initially sampled timestamp. The service processor determines if a current time exceeds the check time. In addition, the service processor generates an error log, responsive to a determination that the current time exceeds the check time.

Making Hardware Objects And Operations Thread-Safe

US Patent:
2010027, Oct 28, 2010
Filed:
Apr 27, 2009
Appl. No.:
12/430214
Inventors:
Daniel M. Crowell - Rochester MN, US
Alan Hlava - Mazeppa MN, US
Christopher T. Phan - Rochester MN, US
David D. Sanner - Rochester MN, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:
G06F 9/46
US Classification:
718106
Abstract:
Performance in object-oriented systems may be improved by allowing multiple concurrent hardware control and diagnostic operations to run concurrently on the system while preventing race conditions, state/data corruption, and hangs due to deadlock conditions. Deadlock prevention rules may be employed to grant or deny request for hardware operation locks, hardware communication locks, and/or data locks.

Implementing Authentication Protocol For Merging Multiple Server Nodes With Trusted Platform Modules Utilizing Provisioned Node Certificates To Support Concurrent Node Add And Remove

US Patent:
2020006, Feb 27, 2020
Filed:
Aug 21, 2018
Appl. No.:
16/106069
Inventors:
- Armonk NY, US
Elaine R. Palmer - Hanover NH, US
Kenneth A. Goldman - Norwalk CT, US
William E. Hall - Clinton CT, US
Hugo M. Krawczyk - Tarrytown NY, US
David D. Sanner - Rochester MN, US
Christopher J. Engel - Rochester MN, US
Peter A. Sandon - Essex Junction VT, US
International Classification:
H04L 29/06
H04L 9/08
G06F 9/445
G06F 9/455
G06F 9/4401
Abstract:
A method and computer system for implementing authentication protocol for merging multiple server nodes with trusted platform modules (TPMs) utilizing provisioned node certificates to support concurrent node add and node remove. Each of the multiple server nodes boots an instance of enablement level firmware and extended to a trusted platform module (TPM) on each node as the server nodes are powered up. A hardware secure channel is established between the server nodes for firmware message passing as part of physical configuration of the server nodes to be merged. A shared secret is securely exchanged via the hardware secure channel between the server nodes establishing an initial authentication value shared among all server nodes. All server nodes confirm common security configuration settings and exchange TPM log and platform configuration register (PCR) data to establish common history for future attestation requirements, enabling dynamic changing the server nodes and concurrently adding and removing nodes.

Selection Of A Primary Microprocessor For Initialization Of A Multiprocessor System

US Patent:
2014017, Jun 19, 2014
Filed:
Dec 19, 2012
Appl. No.:
13/719774
Inventors:
- Armonk NY, US
David D. Sanner - Rochester MN, US
Thi N. Tran - Round Rock TX, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:
G06F 15/76
US Classification:
712 30
Abstract:
Embodiments of the present invention provide a method for initializing a plurality of processors of a multi-processor system by executing, at each respective processor of the plurality of processors, at least a portion of local initialization code stored on the respective processor. Receiving, at a designated processor of the plurality of processors, external initialization code stored in external memory, wherein the remainder of the plurality of processors do not have access to the external initialization code stored in external memory. Determining, the designated processor, send at least a portion of the external initialization code to a processor of the remainder of the plurality of processors.

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