Debashis Bhattacharya, Age 632709 Moffett Ct, Plano, TX 75093

6378090, Apr 23, 2002

Apr 23, 1999

09/298018

Debashis Bhattacharya - Plano TX

Texas Instruments Incorporated - Dallas TX

G01R 3128

714724, 714734, 712 38

This invention is a testing technique for an electronic circuit such as an integrated circuit. The electronic circuit includes a JTAG test access port and at least one testable embedded core circuit having its own JTAG compliant second test access port. A test access port controller and a programmable switch control testing of the electronic circuit. An internal state in the test access port controller controls the switch state of the programmable switch. When an embedded core circuit is connected for test, the test access port controller remains responsive to the first test access port and operates in a set of snoopy states corresponding to the state of the embedded core circuit under test. The test access port controller can regain control of the first test access port when in snoopy states. At least one of the embedded core circuits includes a test access port controller for similar controlled connection to further embedded core circuits.

6381717, Apr 30, 2002

Apr 23, 1999

09/298801

Debashis Bhattacharya - Plano TX

Texas Instruments Incorporated - Dallas TX

G01R 3128

714724, 714734, 712227

This invention is a testing technique for an electronic circuit such as an integrated circuit. The electronic circuit includes a JTAG test access port and at least one testable embedded core circuit having its own JTAG compliant second test access port. A test access port controller and a programmable switch control testing of the electronic circuit. An internal state in the test access port controller, such as bits in a data register, controls the switch state of the programmable switch. When an embedded core circuit is connected for test, the test access port controller remains responsive to the first test access port and operates in a set of snoopy states corresponding to the state of the embedded core circuit under test. The test access port controller can regain control of the test access port and disconnect all of the embedded core circuits when in snoopy states upon detection of a wake-up instruction loaded into a snoopy instruction register during a snoopy state corresponding to an instruction input state. Alternatively, a count of instruction bits more than the most bits for instruction input for any embedded core can trigger the wake-up function.

6425100, Jul 23, 2002

Apr 23, 1999

09/298138

Debashis Bhattacharya - Plano TX

Texas Instruments Incorporated - Dallas TX

G06R 3128

714724, 714734, 712 38

This invention is a testing technique for an electronic circuit such as an integrated circuit. The electronic circuit includes a JTAG test access port and at least one testable embedded core circuit having its own JTAG compliant second test access port. A test access port controller and a programmable switch control testing of the electronic circuit. An internal state in the test access port controller controls the switch state of the programmable switch. The programmable switch is controlled to selectively connect the first test access port to the embedded core circuits. When an embedded core circuit is connected for test, the test access port controller remains responsive to the first test access port and operates in a set of snoopy states corresponding to the state of the embedded core circuit under test. The test access port controller can regain control of the first test access port and disconnect all of the embedded core circuits when in snoopy states. The electronic circuit may include a non-testable embedded core circuit whose test is controller by the test access port controller.

6782514, Aug 24, 2004

Jan 24, 2002

10/056343

Debashis Bhattacharya - Plano TX
Vamsi Boppana - Santa Clara CA

Zenasis Technologies, Inc. - Campbell CA

G06F 1750

716 3, 716 2, 716 18, 716 7, 716 17

The present invention relates to a method for minimizing the number of standard cells required to implement a digital circuit and for improving the characterization of new standard cells based on their context/environment. In addition, a systematic method that utilizes detailed characterization at the transistor-level on critical areas of the design for improved characterization and optimization of the entire design is presented.

6938223, Aug 30, 2005

Feb 15, 2002

10/076809

Vamsi Boppana - Santa Clara CA, US
Debashis Bhattacharya - Plano TX, US

Zenasis Technologies, Inc. - Campbell CA

G06F017/50
G06F007/38

716 1, 716 2, 716 5, 716 7, 708232

A method and system for constructing, designing, and using a family of logic circuits based on methods of interconnecting transistors (or more generally, switches). The method includes the selective use of functionally redundant transistors to achieve target objectives, such as speed of operation, power dissipation, control over switching capacitances, noise characteristics and signal integrity. In accordance with the present invention, multiple topologies may be incorporated into the implementation of a single dynamic transistor topology. The logic circuit family provides flexibility by implementing different topologies for the various functionally redundant sub-networks of transistors. The method is applicable to any network of transistors whose characteristics depend, at least in part, on its implementation topology.

7003738, Feb 21, 2006

Jun 29, 2001

09/896071

Debashis Bhattacharya - Plano TX, US
Vamsi Boppana - Santa Clara CA, US
Rajeev Murgai - Santa Clara CA, US
Rabindra Roy - Hillsboro OR, US

Zenasis Technologies, Inc. - Campbell CA

G06F 17/50

716 1, 716 2, 716 5, 716 11

The present invention pertains to an automated method for designing a integrated circuit (IC) design-specific cell, the method includes the steps of receiving a design specification for the design-specific cell, mapping a transistor-level representation of the design-specific cell, wherein the mapping is based on at least one, but perhaps plural design specifications, and evaluating the transistor-level representation of the design-specific cell for satisfaction of the design specification.

7225423, May 29, 2007

Jun 29, 2001

09/896059

Debashis Bhattacharya - Plano TX, US
Vamsi Boppana - Santa Clara CA, US
Rabindra Roy - Hillsboro OR, US
Jayanta Roy - San Jose CA, US

Zenasis Technologies, Inc. - San Jose CA

G06F 17/50

716 18, 716 7

A system and method for designing ICs, including the steps of: analyzing and optimizing a target IC design based on design-specific objectives; partitioning the optimized target IC design into pre-defined standard-cells from one or more libraries and creating design-specific cells specifically having unique functionality and characteristics not found amongst the standard-cells; identifying and determining a minimal subset of the standard-cells and design-specific cells, the interconnection of which represents the target IC design; generating the necessary views, including layout and characterizing of the design-specific cells included in a unique, minimal subset, wherein the IC design is subject to objectives and constraints of the target IC.

2010024, Sep 23, 2010

Mar 20, 2009

12/408534

Swati Bhattacharyya - Plano TX, US
Supratik Mukhopadhyay - Providence UT, US
Debashis Bhattacharya - Plano TX, US

Simbiosys Biowares, Inc. - Dallas TX

C12Q 1/02
C12M 1/34

435 29, 4352871

A method for predetermining whether a cancer has a probability to become metastatic or recurrent, having the steps of: obtaining a sample cell population; assaying the sample cell population; detecting the rate of change of the sample cell population's pH over time; and comparing the pH change versus a predetermined pH rate of change. Also provided is a method of treating a patient having the steps of: isolating a cancer stem cell from a patient; culturing the cancer stem cell to produce a pool of descendant cells; culturing cells from the pool of descendant cells in the presence at least one compound among: anti-cancer drugs, myeloablative, chemotherapeutic, and immunotherapeutic agents, and a combination thereof; assaying over time, during the step of culturing, hydrogen ion concentration in the set of cells; and selecting a candidate therapeutic regimen for the patient based on a result of the assaying step.