Dennis W Hollenbeck DeceasedSan Jose, CA

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Publications & IP owners

Us Patents

Self-Test Subsystem For Nuclear Reactor Protection System

US Patent:
4517154, May 14, 1985
Filed:
Jul 27, 1982
Appl. No.:
6/402053
Inventors:
Ulric E. Dennis - San Jose CA
Dennis W. Hollenbeck - San Jose CA
John A. Kirtland - San Jose CA
Kenneth B. Stackhouse - San Jose CA
Patricia A. Wilson - San Jose CA
William D. Hill - San Jose CA
David D. Akers - Los Gatos CA
Elmer D. Hill - Sacramento CA
Assignee:
General Electric Company - San Jose CA
International Classification:
G21C 1700
US Classification:
376259
Abstract:
A self-test system for a nuclear power plant, nuclear reactor protection system is disclosed. Nuclear protection systems are the electronic controls, typically including circuit cards, located intermediate between sensors (as for detecting core overheat) and a control (as for providing rod injection to shut down a reactor). Constant surveillance of the nuclear system protection system is provided by a microprocessor that serially addresses protection system circuit cards and loads them at pre-determined input points with test commands. The addressed cards are thereafter simultaneously activated by a system-wide command. The test command is a pulse which is so short in duration that its affect is transparent to the system and cannot cause overall system operation. The pulse passes through the actuating electrical components to verify, on the real actuating path, the operating integrity of the system. After an appropriate response interval, the output state of the system is recorded in system-wide resident registers.

Testable Optically Isolated Control Circuit

US Patent:
4498196, Feb 5, 1985
Filed:
Jul 27, 1982
Appl. No.:
6/402368
Inventors:
Peter W. Holoyda - San Jose CA
Dennis W. Hollenbeck - San Jose CA
William D. Hill - San Jose CA
Assignee:
General Electric Company - San Jose CA
International Classification:
H04B 900
US Classification:
455607
Abstract:
A testable physically isolated control circuit includes a first unit 10, a second unit 40, and an optical coupler 30 to couple units 10 and 40 together. The functional portion 10a of the first unit includes an input terminal 11 and an oscillator 12 for controlling a first transmitter 17. Signals from the first transmitter are received by a receiver 44 in unit 40 to control the relay 48. Each unit 10 and 40 also includes a testing portion 10b and 40b for monitoring the condition of the functional portions. The testing portion 40b detects the state of the receiver 44 and the relay 48 and transmits this information via transmitter 65 to a receiver 22 in first unit 10. This receiver 22 controls input terminals 29 and 15 to provide control information concerning the proper functioning of the circuit.

Load Driving Circuitry With Load Current Sensing

US Patent:
4485342, Nov 27, 1984
Filed:
Jul 27, 1982
Appl. No.:
6/402373
Inventors:
William D. Hill - San Jose CA
Dennis W. Hollenbeck - San Jose CA
Kenneth M. Schor - Sudbury MA
Assignee:
General Electric Company - San Jose CA
International Classification:
H02J 300
H01H 4728
US Classification:
323351
Abstract:
A testable load driving circuit apparatus includes a solid-state load driver for controlling AC current loads coupled in series with a winding of a saturable core reactor used for sensing the presence or absence of load current through a load current monitor which is coupled to another winding in the reactor. The load driving circuitry may be tested during circuit operation by injecting a signal of insufficient duration to substantially affect the load circuit.

Media Defect Management Within Disk Drive Sector Format

US Patent:
4914530, Apr 3, 1990
Filed:
Sep 21, 1987
Appl. No.:
7/098913
Inventors:
Randolph H. Graham - Fremont CA
Dennis W. Hollenbeck - Santa Clara CA
Assignee:
Plus Development Corporation - Milpitas CA
International Classification:
G11B 509
US Classification:
360 48
Abstract:
In a rotating disk drive for storing and retrieving data used by a host system computer, a narrow gap is provided within a data sector format for each concentric data track of the drive. This gap may be normally located at the end of the track, in a speed tolerance buffer region following the last sector. In the event a media defect is detected which otherwise falls within a NAR area for a particular sector, this gap may be shifted to the beginning of the data track, thereby shifting all of the sectors and their NAR areas backward by the width of the gap. The media defect otherwise falling into the NAR area of a particular sector then falls harmlessly into a data field of a preceding sector, and this preceding sector may then be read and mapped out of service by insertion of a spare sector within the physical track without any loss of user data storage capability.

Testable Optically Isolated Control Circuit

US Patent:
4495655, Jan 22, 1985
Filed:
Nov 15, 1982
Appl. No.:
6/442395
Inventors:
Michael R. Benson - San Jose CA
William D. Hill - San Jose CA
Garrett G. OBrien - San Jose CA
Dennis W. Hollenbeck - San Jose CA
Assignee:
General Electric Company - San Jose CA
International Classification:
H04B 900
US Classification:
455603
Abstract:
A testable physically isolated control circuit includes a first unit 10, a second unit 40, and an optical coupler 30 to couple units 10 and 40 together. The functional portion 10a of the first unit includes an input terminal 11 and an oscillator 12 for controlling a first transmitter 17. Signals from the first transmitter are received by a receiver 44 in unit 40 to control the relay 48. Each unit 10 and 40 also includes a testing portion 10b and 40b for monitoring the condition of the functional portions. The testing portion 40b detects the state of the receiver 44 and the relay 48 and transmits this information via transmitter 65 to a receiver 22 in first unit 10. This receiver 22 controls input terminals 29 and 15 to provide control information concerning the proper functioning of the circuit.

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