Dhananjay A Joshi, Age 5314364 NW Lilium Dr, Portland, OR 97229

2008023, Sep 25, 2008

Mar 22, 2007

11/726563

Sin Tan - Portland OR, US
Kai Cheng - Portland OR, US
Rajesh S. Pamujula - Hillsboro OR, US
Sivakumar Radhakrishnan - Portland OR, US
Dhananjay Joshi - Beaverton OR, US

G06F 13/28

711146

A bridge includes a memory to establish a transaction table and write combining windows. Each write combining window is associated with a cache line and is subdivided into subwindows; and each of the subwindows is associated with a partial cache line. The bridge includes a controller to determine whether an incoming partial write transaction conflicts with a transaction stored in the transaction table. If a conflict occurs, the controller uses the write combining windows to combine the partial write transaction with another partial write transaction if one of the partial write combining windows is available. The controller issues a retry signal to a processor originating the partial write transaction if none of the partial write combining windows are available.

2023004, Feb 9, 2023

Dec 22, 2021

17/559612

- SANTA CLARA CA, US
Dhananjay JOSHI - Portland OR, US
Philip LANTZ - Cornelius OR, US
Rajesh SANKARAN - Portland OR, US
Narayan RANGANATHAN - Bangalore, IN

G06F 9/48
G06F 9/455
G06F 9/30

Apparatus and method for managing pipeline depth of a data processing device. For example, one embodiment of an apparatus comprises: an interface to receive a plurality of work requests from a plurality of clients; and a plurality of engines to perform the plurality of work requests; wherein the work requests are to be dispatched to the plurality of engines from a plurality of work queues, the work queues to store a work descriptor per work request, each work descriptor to include information needed to perform a corresponding work request, wherein the plurality of work queues include a first work queue to store work descriptors associated with first latency characteristics and a second work queue to store work descriptors associated with second latency characteristics; engine configuration circuitry to configure a first engine to have a first pipeline depth based on the first latency characteristics and to configure a second engine to have a second pipeline depth based on the second latency characteristics.

2023004, Feb 9, 2023

Dec 22, 2021

17/560170

- Santa Clara CA, US
Philip LANTZ - Cornelius OR, US
Sanjay KUMAR - Hillsboro OR, US
Rajesh SANKARAN - Portland OR, US
Narayan RANGANATHAN - Bangalore, IN
Saurabh GAYEN - Portland OR, US
Dhananjay JOSHI - Portland OR, US
Nikhil P. RAO - Bengaluru, IN

G06F 11/07

Apparatus and method for high-performance page fault handling. For example, one embodiment of an apparatus comprises: one or more accelerator engines to process work descriptors submitted by clients to a plurality of work queues; fault processing hardware logic associated with the one or more accelerator engines, the fault processing hardware logic to implement a specified page fault handling mode for each work queue of the plurality of work queues, the page fault handling modes including a first page fault handling mode and a second page fault handling mode.

2023003, Feb 2, 2023

Jul 27, 2022

17/875198

- Santa Clara CA, US
Philip R. Lantz - Cornelius OR, US
Narayan Ranganathan - Bangalore, IN
Saurabh Gayen - Portland OR, US
Sanjay Kumar - Hillsboro OR, US
Nikhil Rao - Bengaluru, IN
Dhananjay A. Joshi - Portland OR, US
Hai Ming Khor - Hillsboro OR, US
Utkarsh Y. Kakaiya - Folsom CA, US

Intel Corporation - Santa Clara CA

G06F 3/06

Methods and apparatus relating to data streaming accelerators are described. In an embodiment, a hardware accelerator such as a Data Streaming Accelerator (DSA) logic circuitry provides high-performance data movement and/or data transformation for data to be transferred between a processor (having one or more processor cores) and a storage device. Other embodiments are also disclosed and claimed.

2023003, Feb 2, 2023

Apr 1, 2022

17/711928

- Santa Clara CA, US
Philip R. Lantz - Cornelius OR, US
Rajesh M. Sankaran - Portland OR, US
Sanjay Kumar - Hillsboro OR, US
Saurabh Gayen - Portland OR, US
Nikhil Rao - Bengaluru, IN
Utkarsh Y. Kakaiya - Folsom CA, US
Dhananjay A. Joshi - Portland OR, US
David Jiang - Chandler AZ, US
Ashok Raj - Portland OR, US

Intel Corporation - Santa Clara CA

G06F 3/06
G06F 9/455

Methods and apparatus relating to scalable access control checking for cross-address-space data movement are described. In an embodiment, a memory stores an InterDomain Permissions Table (IDPT) having a plurality of entries. At least one entry of the IDPT provides a relationship between a target address space identifier and a plurality of requester address space identifiers. A hardware accelerator device allows access to a target address space, corresponding to the target address space identifier, by one or more of requesters, corresponding to the plurality of requester address space identifiers, respectively, based at least in part on the relationship provided by the at least one entry of the IDPT. Other embodiments are also disclosed and claimed.

2021014, May 20, 2021

Dec 21, 2020

17/129496

- Santa Clara CA, US
Philip R. Lantz - Cornelius OR, US
Dhananjay A. Joshi - Portland OR, US
Rupin H. Vakharwala - Hillsboro OR, US
Rajesh M. Sankaran - Portland OR, US
Narayan Ranganathan - Bangalore, IN
Sanjay Kumar - Hillsboro OR, US

Intel Corporation - Santa Clara CA

G06F 12/10
G06F 12/0875
G06F 13/28
G06F 13/40
G06F 13/42

Techniques for offload device address translation fetching are disclosed. In the illustrative embodiment, a processor of a compute device sends a translation fetch descriptor to an offload device before sending a corresponding work descriptor to the offload device. The offload device can request translations for virtual memory address and cache the corresponding physical addresses for later use. While the offload device is fetching virtual address translations, the compute device can perform other tasks before sending the corresponding work descriptor, including operations that modify the contents of the memory addresses whose translation are being cached. Even if the offload device does not cache the translations, the fetching can warm up the cache in a translation lookaside buffer. Such an approach can reduce the latency overhead that the offload device may otherwise incur in sending memory address translation requests that would be required to execute the work descriptor.