Trang Ta, Age 5215305 Cadoz Dr, Austin, TX 78728

5764083, Jun 9, 1998

Jun 10, 1996

8/664966

Bang T. Nguyen - Austin TX
Mark Daniel Papermaster - Austin TX
Giao Ngoc Pham - Portland OR
Trang Khanh Ta - Austin TX
Willem Bernard van der Hoeven - Round Rock TX

International Business Machines Corporation - Armonk NY

H03K 1900

326 93

A system for clocking self resetting CMOS (SRCMOS) circuits operating at high speed includes a clock generator circuit which produces a first pipeline clock pulse of relatively narrow width from a leading edge of a system clock having a relatively long duration with respect to the first pipeline clock, a number of delay circuits, the time duration of each of the delay circuits being determined by characteristics of evaluation logic in the SRCMOS circuits being clocked, the delay circuits being connected in a serial pipeline fashion such that each subsequent delayed clock pulse overlaps a preceding clock pulse by at least a predetermined minimum time duration. The clocking system also includes a cycle relax mode whereby the clock pulse output of the clock generator circuit may be extended for test or diagnostic purposes.

5383155, Jan 17, 1995

Nov 8, 1993

8/148601

Trang K. Ta - Austin TX

International Business Machines Corporation - Armonk NY

G11C 700

365191

Control circuit and control processing for a memory system having a system data bus coupled to at least one data output latch. The control circuit and process generate a read command (RC) to enable the at least one data output latch to latch data from the system data bus in response to a read clock signal (RCLK). The read command (RC) occurs substantially simultaneous with the instant that a valid data state exists on the system data bus and is developed without directly monitoring the system data bus. Upon detecting the read clock signal (RCLK) a latch enable signal is generated. A valid data signal is next generated independent of the system data bus through the use of a dummy circuit having multiple dummy cells, dummy bitlines and a common dummy bus. The valid data signal can be generated either simultaneous with the instant of valid data development on the system data bus or can precede the instant of valid data development by a predetermined small interval of time predefined through the system architecture. The read command (RC) is generated upon occurrence of both the latch enable signal and the valid data signal.