Dominic Joseph Schepis, Age 69890 Hillside Rd, New Hamburg, NY 12590

6339005, Jan 15, 2002

Oct 22, 1999

09/425394

Andres Bryant - Essex Junction VT
Jerome B. Lasky - Essex Junction VT
Effendi Leobandung - Wappingers Falls NY
Dominic J. Schepis - Wappingers Falls NY

International Business Machines Corporation - Armonk NY

H01L 21336

438307, 438163, 438233

A silicon on insulator transistor is disclosed which has a Schottky contact to the body. The Schottky contact may be formed on the source and/or drain side of the gate conductor. A spacer, with at least a part thereof being disposable, is formed on the sidewalls of the gate conductor. Extension regions are provided in the substrate which extend under the spacer and the gate conductor. Source and drain diffusion regions are implanted into the substrate adjacent to the extension regions. The disposable part of the spacer is then removed to expose a portion of the extension region. A metal layer is formed at least in the extension regions, resulting in the Schottky contact.

6352905, Mar 5, 2002

Nov 1, 2000

09/702787

Dominic J. Schepis - Wappingers falls NY
Steven H. Voldman - South Burlington VT

International Business Machines Corporation - Armonk NY

H01L 2176

438404, 438405, 438406

A method and structure for forming an integrated circuit wafer comprises forming a substrate having first and second portions, depositing a first insulator over the substrate, patterning the first insulator such that the first insulator remains only over the first portion, depositing a second insulator over substrate (the first insulator has different thermal dissipation characteristics than the second insulator), polishing the second insulator to form a planar surface, and attaching a silicon film over the first insulator and the second insulator.

6387742, May 14, 2002

May 23, 2001

09/862451

Dominic J. Schepis - Wappingers Falls NY
William R. Tonti - Essex Junction VT
Steven H. Voldman - South Burlington VT

International Business Machines Corporation - Armonk NY

H01L 21336

438197, 438294, 438311, 438430

Silicon is formed at selected locations on a substrate during fabrication of selected electronic components. A dielectric separation region is formed within the top silicon layer, and filled with a thermally conductive material. A liner material may be optionally deposited prior to depositing the thermally conductive material. In a second embodiment, a horizontal layer of thermally conductive material is also deposited in an oxide layer or bulk silicon layer below the top layer of silicon.

6395587, May 28, 2002

Feb 11, 2000

09/502809

Scott Crowder - Ossining NY
Dominic J. Schepis - Wappingers Falls NY
Melanie J. Sherony - Wappingers Falls NY

International Business Machines Corporation - Armonk NY

H01L 2100

438149, 438144

A semiconductor device having a silicon-on-insulator (SOI) structure includes a field-effect transistor having amorphized source and drain regions formed by implanting silicon or germanium ions into a silicon layer formed over a buried insulator. The fully amorphized source and drain regions ultimately result in permanent crystalline defects that cause p-n junction leakage which allows charge in the body of the device to dissipate, thereby improving the overall efficiency and performance of the device. The source and drain regions are amorphized throughout their entire thickness to prevent single crystal re-crystallization from occurring during annealing and other subsequent processing steps that can degrade the quality of the p-n leakage junctions.

6404014, Jun 11, 2002

Nov 8, 2000

09/708337

Effendi Leobandung - Wappingers Falls NY
Devendra K. Sadana - Pleasantville NY
Dominic J. Schepis - Wappingers Falls NY
Ghavam Shahidi - Elmsford NY

International Business Machines Corporation - Armonk NY

H01L 2701

257347, 257 67

A planar silicon-on-insulator (SOI) structure and a process for fabricating the structure. The SOI structure has a silicon wafer, an oxide layer, and a silicon layer. Trenches are formed, extending from the top surface of the structure to the silicon wafer, and are filled with a semiconductor. The trenches have a top, a bottom, and side walls. The side walls have side-wall silicon portions. The side-wall silicon portions of the trench side walls are covered by trench side-wall oxide layers. A protective side wall extends over the trench side walls and trench side-wall oxide layers from the trench top to the trench bottom.

6429084, Aug 6, 2002

Jun 20, 2001

09/885828

Heemyong Park - LaGrangeville NY
Fariborz Assaderaghi - San Diego CA
Dominic J. Schepis - Wappingers Falls NY

International Business Machines Corporation - Armonk NY

H01L 21336

438305, 438300, 438424, 438479, 438589

In raised source/drain CMOS processing, the prior art problem of lateral epi growth on the gate stack interfering physically with the raised S/D structures and producing device characteristics that vary along the length of the gate and the problem of overetch of the STI oxide during the preclean step is solved by using a sacrificial nitride layer to block both the STI region and the gate stack, together with a process sequence in which the halo and extension implants are performed after the S/D implant anneal.

6429488, Aug 6, 2002

Feb 22, 2001

09/791273

Effendi Leobandung - Wappingers Falls NY
Devendra K. Sadana - Pleasantville NY
Dominic J. Schepis - Wappingers Falls NY
Ghavam G. Shahidi - Yorktown Heights NY

International Business Machines Corporation - Armonk NY

H01L 2712

257354, 438413, 438478, 438479, 257296, 257347

A process for making a SOI region and a bulk region in a semiconductor device. The process includes providing a SOI structure. The SOI structure has a thin silicon layer, a buried insulating oxide layer underlying the thin silicon layer, and a silicon substrate underlying the buried insulating oxide layer. Next, a nitride layer is deposited on top of the SOI structure. The SOI structure is exposed by selectively etching portions of the nitride layer. The portion of the nitride layer which is not etched forms the SOI region. The silicon substrate is exposed by selectively etching the remaining portion of the exposed SOI structure. An epitaxial layer is grown on top of the exposed silicon substrate to form the bulk region. The nitride portion above the SOI structure is finally removed.

6437377, Aug 20, 2002

Jan 24, 2001

09/768525

Atul C. Ajmera - Wappingers Falls NY
Victor Ku - Tarrytown NY
Dominic J. Schepis - Wappingers Falls NY

International Business Machines Corporation - Armonk NY

H01L 2710

257204, 257408, 257336

A notched gate MOS device includes either an encapsulated low dielectric material or encapsulated air or a vacuum at the bottom of a notched gate. Due to the low dielectric constant at the site of interface between the gate and the source/drain, the capacitance loss at that site is significantly reduced.