Donald B Gabrielson, Age 6512666 Morningside Dr, Merrifield, MN 56465

7290194, Oct 30, 2007

Dec 17, 2004

11/016192

Donald Gabrielson - Rochester MN, US
Todd Youngman - Rochester MN, US
John Nordman - Rochester MN, US
Michael A. Minter - Bowling Green KY, US

LSI Corporation - Milpitas CA

G01R 31/28

714742

A tool for facilitating automatic test pin assignment for a programmable platform device including a process for collecting information related to the programmable platform device, a process for automatically initializing a test pin assignment for the programmable platform device, a process configured to receive user specifications for IOs and a process for performing dynamic test pin reassignment in response to the user specifications.

7340700, Mar 4, 2008

May 27, 2005

11/140392

Steven Emerson - Chanhassen MN, US
Jonathan Byrn - Kasson MN, US
Donald Gabrielson - Rochester MN, US
Gary Lippert - Kasson MN, US

LSI Logic Corporation - Milpitas CA

G06F 17/50

716 4

A system for RTL test insertion in an integrated circuit layout pattern includes a core module, a test wrapper, and a smart wrapper. The core module describes a function defined by logical elements, interconnections between logical elements, input pins and output pins. The test wrapper is adapted to encapsulate the core module and to create test pins representing the core module. The smart wrapper is adapted to encapsulate the test wrapper and to assign the test pins to a non-asserted state. The smart wrapper is adapted to place an assertion on one or more of the test pins for static or dynamic testing of the integrated circuit layout pattern.

2004025, Dec 16, 2004

Jun 11, 2003

10/459158

Jonathan Byrn - Kasson MN, US
James Jensen - Eagan MN, US
Roy Perrigo - Henrietta NY, US
Donald Gabrielson - Rochester MN, US

G06F019/00

702/117000

The present invention is directed to a method and an apparatus for automatically configuring and/or inserting chip resources for manufacturing tests. A maximum test configuration (“test backplane”) for all IP blocks is created and loaded into a tool suite. When a user issues a request to consume some IP blocks, the request may be checked for legality within the “test backplane”. If a test resource (IP block) is not available for activation, then either the test resource may not be activated or the conflicting resource problem must be resolved so that the test resource may be activated. This may avoid late design surprises. The resources on the platform may already have test structures associated with them. All of these test structures may be associated with the “test backplane”. These pre-exiting test structures may then be connected.

2007004, Feb 22, 2007

Aug 16, 2005

11/204514

Michael Minter - Bowling Green KY, US
Donald Amundson - New Prague MN, US
Donald Gabrielson - Rochester MN, US

G06F 17/50

716008000

A design tool includes a first module, a second module, a third module and a fourth module. The first module may be configured to select a platform for implementing an integrated circuit design in response to input from a user. The second module may be configured to select a macro block to be placed on the platform in response to input from the user. A description of the macro block may be configured to indicate whether the macro block has connectivity placement data. The third module may be configured to determine whether the macro block has the connectivity placement data based on the description of the macro block. The fourth module may be configured to automatically place the macro block on the platform based on the connectivity placement data, when the description of the macro block indicates the connectivity placement data is present.