Duane H Oto563 Dawn Dr, Sunnyvale, CA 94087
Duane Oto Phones & Addresses
563 Dawn Dr, Sunnyvale, CA 94087 (408) 730-1138
5994 Dewey Blvd, Sacramento, CA 95824
Santa Clara, CA
563 Dawn Dr, Sunnyvale, CA 94087
Work
Position:
Professional/Technical
Education
Degree:
High school graduate or higher
Mentions for Duane H Oto
Publications & IP owners
Us Patents
Mos Voltage Divider Structure Suitable For Higher Potential Feedback Regulation
US Patent:
4527180, Jul 2, 1985
Filed:
Jan 31, 1983
Appl. No.:
6/462192
Inventors:
Duane Oto - Santa Clara CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 2704
H01G 438
H02M 508
H01G 438
H02M 508
US Classification:
357 236
Abstract:
An MOS voltage divider is described which is particularly useful for dividing a relatively high voltage (e. g. , 21 volts). Capacitance division is employed, thus, the divider consumes substantially no current. Capacitors are fabricated from first and second layers of polysilicon and an intermediate layer of silicon dioxide. Common centroid geometry is used to compensate for process variations.
Self-Limiting Erase Scheme For Eeprom
US Patent:
4797856, Jan 10, 1989
Filed:
Apr 16, 1987
Appl. No.:
7/039086
Inventors:
Winston K. M. Lee - San Francisco CA
Duane H. Oto - Santa Clara CA
Simon M. Tam - San Mateo CA
Duane H. Oto - Santa Clara CA
Simon M. Tam - San Mateo CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G11C 700
G11C 1140
G11C 1140
US Classification:
365185
Abstract:
A self-limiting scheme to prevent an over-erase condition of a one-transistor EEPROM cell. During an erase cycle, a drain voltage is fed back to a floating gate to counteract a positive erase voltage on the source of the memory cell and therein reduce the electric field across the tunnel oxide leading to the cessation of erase. In another scheme, the drain voltage is fed back to deactivate the erase voltage when a predetermined drain voltage value is exceeded.
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