People Background Check
Find People:

Dustin A Woodbury14 Inwood Way, Melbourne, FL 32937

Get Report
Known as:
A Dustin A N Dustin A Dr Woodbury Dustin Andrew Woodbury Dusty Woodbury

Dustin Woodbury Phones & Addresses

14 Inwood Way, Indian Harbour Beach, FL 32937 (321) 777-7621

Palm Bay, FL

Jacksonville, FL

14 Inwood Way, Indian Harbour Beach, FL 32937 (321) 544-4960

Social networks

Dustin A Woodbury

Linkedin

Work

Company: Smart teacher smart kid Mar 2006 Position: Tutor

Education

Degree: Doctorates, Doctor of Philosophy Specialities: Physics

Emails

d***[email protected]

Industries

Education Management

Mentions for Dustin A Woodbury

Dustin Woodbury resumes & CV records

Resumes

Dustin Woodbury Photo 22

Tutor

Location:
Satellite Beach, FL
Industry:
Education Management
Work:
Smart Teacher Smart Kid
Tutor Harris Semiconductor/Intersil Jul 1984 - Oct 2005
Senior Engineer General Dynamics Sep 1979 - Jun 1984
Engineer Rice Univ Sep 1977 - Sep 1979
Research Fellow and Post Doctoral

Publications & IP owners

Us Patents

Method For Making A Diffused Back-Side Layer On A Bonded-Wafer With A Thick Bond Oxide

US Patent:
6362075, Mar 26, 2002
Filed:
Jun 30, 1999
Appl. No.:
09/345261
Inventors:
Joseph A. Czagas - Palm Bay FL
Dustin A. Woodbury - Indian Harbour Beach FL
James D. Beasom - Melbourne Village FL
Assignee:
Harris Corporation - Melbourne FL
International Classification:
H01L 2100
US Classification:
438455, 438456, 438408, 438164, 438933
Abstract:
Integrated circuits, semiconductor devices and methods for making the same are described. Each embodiment shows a diffused, doped backside layer in a device wafer that is oxide bonded to a handle wafer. The diffused layer may originate in the device wafer, in the handle wafer, in the bond oxide or in an additional semiconductor layer of polysilicon or epitaxial silicon. The methods use a thermal bond oxide or a combination of a thermal and a deposited oxide.

Wafer Trench Article And Process

US Patent:
6365953, Apr 2, 2002
Filed:
Apr 1, 1999
Appl. No.:
09/283530
Inventors:
Patrick Anthony Begley - West Melbourne FL
Donald Frank Hemmenway - Melbourne FL
George Bajor - Melbourne FL
Anthony Lee Rivoli - Palm Bay FL
Jeanne Marie McNamara - Palm Bay FL
Michael Sean Carmody - Palm Bay FL
Dustin Alexander Woodbury - Indian Harbour Beach FL
Assignee:
Intersil Americas Inc. - Irvine CA
International Classification:
H01L 2900
US Classification:
257513, 257506, 257510, 257520
Abstract:
A bonded wafer has a device substrate with isolation trenches defining device regions Oxide dogbone structures are removed before filling trenches Voids in the trenches are spaced from the top of the trenches. The trenches are covered with an oxide layer and filled with polysilicon A LOCOS mask structure comprising a layer of CVD pad oxide and silicon nitride cover the trenches and the adjacent device substrate regions.

Method Of Forming Resistive Contacts On Intergrated Circuits With Mobility Spoiling Ions Including High Resistive Contacts And Low Resistivity Silicide Contacts

US Patent:
6403472, Jun 11, 2002
Filed:
Jun 23, 1999
Appl. No.:
09/339274
Inventors:
Dustin A. Woodbury - Indian Harbour Beach FL
Joseph A. Czagas - Palm Bay FL
Assignee:
Harris Corporation - Melbourne FL
International Classification:
H01L 214763
US Classification:
438642, 438643, 438651, 438653
Abstract:
A semiconductor device or integrated circuit has high and low resistive contacts. Mobility spoiling species such as carbon or oxygen are implanted into all contacts. The high resistive contacts are covered with a barrier metal to protect silicide from chemical interaction with the interconnect metalization (aluminum) in the low-resistance contacts. Selective silicide formation converts some of the contacts back to low-resistance contacts.

Wafer Trench Article And Process

US Patent:
6551897, Apr 22, 2003
Filed:
Nov 16, 2001
Appl. No.:
09/993968
Inventors:
Patrick Anthony Begley - West Melbourne FL
Donald Frank Hemmenway - Melbourne FL
George Bajor - Melbourne FL
Anthony Lee Rivoli - Palm Bay FL
Jeanne Marie McNamara - Palm Bay FL
Michael Sean Carmody - Palm Bay FL
Dustin Alexander Woodbury - Indian Harbour Beach FL
Assignee:
Intersil Americas Inc. - Irvine CA
International Classification:
H01L 21762
US Classification:
438404, 438406, 438437
Abstract:
A bonded wafer has a device substrate with isolation trenches defining device regions Oxide dogbone structures are removed before filling trenches. Voids in the trenches are spaced from the top of the trenches. The trenches are covered with an oxide layer and filled with polysilicon A LOCOS mask structure comprising a layer of CVD pad oxide and silicon nitride cover the trenches and the adjacent device substrate regions.

Highly Linear Integrated Resistive Contact

US Patent:
6667523, Dec 23, 2003
Filed:
Apr 12, 2002
Appl. No.:
10/121412
Inventors:
Dustin A. Woodbury - Indian Harbor Beach FL
Joseph A. Czagas - Palm Bay FL
Assignee:
Intersil Americas Inc. - Palm Bay FL
International Classification:
H01L 2976
US Classification:
257382, 257 4, 257379, 257384, 257536, 257617, 257914
Abstract:
A semiconductor device or integrated circuit has high and low resistive contacts. Mobility spoiling ions such as carbon are implanted into all contacts of the substrate. High resistive contacts are temporarily covered with an oxide during processing to prevent silicide from forming due to interaction between a siliciding metal and the implanted mobility spoiling ions in the contacts. The resulting high resistance contacts have highly linear I-V curves, even at high voltages. Selective silicide formation converts some of the contacts back to low resistance contacts as a result of interaction between a siliciding metal and the implanted mobility spoiling ions in the low resistance contacts.

Integrated Circuit Having A Device Wafer With A Diffused Doped Backside Layer

US Patent:
6867495, Mar 15, 2005
Filed:
Sep 24, 2001
Appl. No.:
09/961613
Inventors:
Joseph A. Czagas - Palm Bay FL, US
Dustin A. Woodbury - Indian Harbour Beach FL, US
James D. Beasom - Melbourne Village FL, US
Assignee:
Intersil Americas Inc. - Milpitas CA
International Classification:
H01L023/48
H01L027/01
H01L021/76
H01L021/20
US Classification:
257760, 257751, 257758, 257347, 257349, 438406, 438393, 438355, 438458
Abstract:
Integrated circuits, semiconductor devices and methods for making the same are described. Each embodiment shows a diffused, doped backside layer in a device wafer that is oxide bonded to a handle wafer. The diffused layer may originate in the device handle, in the handle wafer, in the bond oxide or in an additional semiconductor layer of polysilicon or epitaxial silicon. The methods use a thermal bond oxide or a combination of a thermal and deposited oxide.

Integrated Circuit Having A Device Wafer With A Diffused Doped Backside Layer

US Patent:
6946364, Sep 20, 2005
Filed:
Feb 13, 2004
Appl. No.:
10/779121
Inventors:
Joseph A. Czagas - Palm Bay FL, US
Dustin A. Woodbury - Indian Harbour Beach FL, US
James D. Beasom - Melbourne Village FL, US
Assignee:
Intersil Americas Inc. - Milpitas CA
International Classification:
H01L021/30
H01L021/22
US Classification:
438455, 438542
Abstract:
Integrated circuits, semiconductor devices and methods for making the same are described. Each embodiment shows a diffused, doped backside layer in a device wafer that is oxide bonded to a handle wafer. The diffused layer may originate in the device handle, in the handle wafer, in the bond oxide or in an additional semiconductor layer of polysilicon or epitaxial silicon. The methods use a thermal bond oxide or a combination of a thermal and deposited oxide.

Radiation Hardened Bipolar Junction Transistor

US Patent:
7029981, Apr 18, 2006
Filed:
Jun 25, 2004
Appl. No.:
10/875731
Inventors:
Nicolaas W. van Vonno - Melbourne FL, US
Dustin Woodbury - Indian Harbour Beach FL, US
Assignee:
Intersil Americas, Inc. - Milpitas CA
International Classification:
H01L 29/732
US Classification:
438326, 438953, 438140, 257630
Abstract:
A method of forming bipolar junction devices, including forming a mask to expose the total surface of the emitter region and adjoining portions of the surface of the base region. A first dielectric layer is formed over the exposed surfaces. A field plate layer is formed on the first dielectric layer juxtaposed on at least the total surface of the emitter region and adjoining portions of the surface of the base region. A portion of the field plate layer is removed to expose a first portion of the emitter surface. A second dielectric layer is formed over the field plate layer and the exposed portion of the emitter. A portion of the second dielectric layer is removed to expose the first portion of the emitter surface and adjoining portions of the field plate layer. A common contact is made to the exposed first portion of the emitter surface and the adjoining portions of the field plate layer. In another embodiment, the field plate and emitter contact are formed simultaneously.

Possible Relatives

David R Woodbury  Debbie C Woodbury  Deborah A Woodbury  Dana P Woodbury  Daniel Woodbury  Derek A Woodbury  Don E Woodbury  Dustin W Johnson  Dustin L Johnston  Dustin W White 

NOTICE: You may not use PeopleBackgroundCheck or the information it provides to make decisions about employment, credit, housing or any other purpose that would require Fair Credit Reporting Act (FCRA) compliance. PeopleBackgroundCheck is not a Consumer Reporting Agency (CRA) as defined by the FCRA and does not provide consumer reports.