Eric MathisenBoca Raton, FL

5630078, May 13, 1997

Jun 20, 1994

8/262397

Daniel P. Fuoco - Boca Raton FL
Luis A. Hernandez - Boca Raton FL
Eric Mathisen - Boca Raton FL
Dennis L. Moeller - Delray Beach FL
Jonathan H. Raymond - Essex Junction VT
Esmaeil Tashakori - Delray Beach FL

International Business Machines Corporation - Armonk NY

G06F 1314

395309

This invention relates to personal computers, and more particularly to personal computers in which capability is provided for continuance of processing through an occurrence of a RESET signal while avoiding systems failures. The personal computer system has a high speed local processor data bus; an input/output data bus; a resettable microprocessor coupled directly to the local processor bus; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and input/output data bus. The bus interface controller provides for arbitration among devices directly coupled to the input/output data bus for access to the input/output data bus and to the local processor bus and for arbitration among the input/output data bus and the microprocessor for access to the local processor bus. The bus interface controller further recognizes receipt of a reset signal intended to initiate a reset of the microprocessor and defers delivery of a reset signal to until the bus interface controller has barred access to the local processor bus and input/output bus by any of the devices potentially requesting such access.

5537600, Jul 16, 1996

May 28, 1991

7/706425

Daniel P. Fuoco - Boca Raton FL
Luis A. Hernandez - Boca Raton FL
Eric Mathisen - Boca Raton FL
Dennis L. Moeller - Delray Beach FL
Jonathan H. Raymond - Essex Junction VT
Esmaeil Tashakori - Delray Beach FL

International Business Machines Corporation - Armonk NY

G06F 1576

395800

This invention relates to personal computers, and more particularly to personal computers in which capability is provided for the usual system controlling processor to be reset, initialized and then isolated if an alternate system controller is provided for the system. In accordance with this invention, a personal computer system has a high speed local processor data bus; an input/output data bus; a microprocessor coupled directly to the local processor bus; a connector coupled directly to the local processor bus for accommodating reception of an alternate processor; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and the input/output data bus, with the bus interface controller providing for detection of the presence of an alternate processor received in the connector and, in response to detection of the presence of an alternate processor, transferring control of the local processor bus from the microprocessor to the alternate processor.

5353417, Oct 4, 1994

May 28, 1991

7/706534

Daniel P. Fuoco - Boca Raton FL
Luis A. Hernandez - Boca Raton FL
Eric Mathisen - Boca Raton FL
Dennis L. Moeller - Delray Beach FL
Jonathan H. Raymond - Essex Junction VT
Esmaeil Tashakori - Delray Beach FL

International Business Machines Corp. - Armonk NY

G06F 1300
G06F 1200

395325

This invention relates to personal computers, and more particularly to personal computers in which arbitration for control over a data handling bus occurs among a plurality of "master" devices coupled directly to the bus and memory address signals are varied in response to such arbitration. The personal computer system has a high speed local processor data bus, an input/output data bus, a microprocessor coupled directly to the local processor bus, volatile memory coupled to the local processor bus for volatile storage of data, and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the buses. The bus interface controller provides for arbitration among devices directly coupled to the input/output data bus for access to the input/output data bus and to the local processor bus, and for arbitration among the input/output data bus and said microprocessor for access to the local processor bus. The bus interface controller is also coupled to the volatile memory for supplying row address select signals to the volatile memory and thereby selecting data storage areas to be accessed, and responds to a change in access granted to the local bus by changing the row address select signal supplied to the volatile memory in preparation for access to potentially different data storage areas of the volatile memory.