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Eric Penn Pettus, Age 507019 Halesboro Dr, Austin, TX 78736

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Known as:
Eric P Pettus Eric Pettis
Related to:
Brian Louis Peterson 48 Jennifer Marie Peterson 44

Eric Pettus Phones & Addresses

1601 Houston St #13, Austin, TX 78756

3401 W Parmer Ln #2714, Austin, TX 78727 (512) 973-9032

5400 W Parmer Ln #1122, Austin, TX 78727

2805 Misty Shore Ln, Pflugerville, TX 78660 (540) 882-3389

38618 John Wolford Rd, Waterford, VA 20197 (540) 521-3446

Pittsburgh, PA

Mentions for Eric Penn Pettus

Eric Pettus resumes & CV records

Resumes

Eric Pettus Photo 20

Senior Software Engineer At Freescale Semiconductor

Position:
Senior Software Engineer at Freescale Semiconductor
Location:
Austin, Texas Area
Industry:
Semiconductors
Work:
Freescale Semiconductor - Austin, Texas Area since Jul 2004
Senior Software Engineer Motorola - Austin, Texas Area Jun 1997 - Jul 2004
CAD Engineer
Education:
Carnegie Mellon University 1993 - 1997
BS, Electrical and Computer Engineering
Skills:
Perl, TCL, LVS, Parasitic Extraction, QRC, Star-RCXT, Calibre, Hercules, EDA, Physical Design, Cadence Virtuoso, ASIC, Cadence, VLSI, IC, Static Timing Analysis, SoC, Semiconductors, ModelSim, Simulations, RC Extraction, Physical Verification, Assura, RCX, PDK Development, PDK, CAD, DRC, Encounter, DesignSync, PERC, Integrated Circuit Design
Languages:
English
Spanish
Eric Pettus Photo 21

Physical Design

Location:
Austin, TX
Industry:
Semiconductors
Work:
Apple
Physical Design Globalfoundries
Smts Design Enablement Methodology Engineer Nxp Semiconductors Dec 2015 - Jul 2016
Senior Physical Design Engineer Freescale Semiconductor Jul 2013 - Dec 2015
Senior Physical Design Engineer Freescale Semiconductor Jul 2004 - Jul 2013
Senior Software Engineer Motorola Jun 1997 - Jul 2004
Software Engineer
Education:
Carnegie Mellon University 1993 - 1997
Bachelors, Bachelor of Science, Computer Engineering
Skills:
Eda, Tcl, Physical Design, Lvs, Perl, Asic, Ic, Parasitic Extraction, Qrc, Star Rcxt, Cadence, Vlsi, Calibre, Integrated Circuit Design, Place and Route, Static Timing Analysis, Cad, Soc, Circuit Design, Physical Verification, Microprocessors, Cadence Encounter, Semiconductors, Rtl Design, Logic Synthesis, Physical Synthesis, Pdk Development, Conformal Lec, Designsync, Cadence Virtuoso, Spice, Assura, Hercules, Rcx, Perc, Verilog, Simulations, Systemverilog, Analog, Modelsim, Debugging, Layout Versus Schematic, Very Large Scale Integration, Design Rule Checking, Application Specific Integrated Circuits, Integrated Circuits, Cmos
Languages:
English
Spanish

Possible Relatives

David C Pettus  Daniel R Pettus  Derek Pettus  Donell Pettus  James E Pettus  Jason C Pettus  Jennifer L Pettus  Eric Z Stander  Eric L Standifer  Eric I Johnston 

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