Fahad Sm Ahmed, Age 451814 Thayer Ave UNIT 4, Los Angeles, CA 90025

2019011, Apr 18, 2019

Apr 26, 2018

15/964050

- San Diego CA, US
Fahad Ahmed - San Diego CA, US
Chulmin Jung - San Diego CA, US

G11C 29/44
G11C 29/10
G11C 29/18
G11C 29/16

A method and apparatus for memory built-in self-test (MBIST) may be configured to load a testing program from an MBIST controller, execute the testing program, and determine and write pass/fail results to a read-out register. For example, in various embodiments, the testing program may comprise one or more write operations that are configured to change data stored in a plurality of memory bitcells from a first value to a second value while a byte enable signal is asserted in order to test stability associated with a memory bitcell, create DC and AC noise due to byte enable mode stress, check at-speed byte enable mode timing, and execute a self-checking algorithm that may be designed to verify whether data is received at a data input (Din) pin. Any memory bitcells storing a value different from an expected value after performing the write operation(s) may be identified as having failed the MBIST.

2017022, Aug 3, 2017

Feb 2, 2016

15/013897

- San Diego CA, US
Fahad AHMED - San Diego CA, US
Sei Seung YOON - San Diego CA, US
Keejong KIM - Phoenix AZ, US

G11C 11/419
G11C 11/418

A memory includes a memory cell, one bitline coupled to the memory cell, a sense amplifier coupled to the one bitline, a timing circuit configured to enable the sense amplifier during a read operation, a control circuit configured to enable the sense amplifier independent of the timing circuit, and a pull-up circuit configured to pull up the one bitline while the sense amplifier is enabled by the control circuit. The method includes enabling a sense amplifier in a read operation by a timing circuit. The sense amplifier is coupled to at least one bitline, and the at least one bitline is coupled to a memory cell. The method further includes enabling the sense amplifier independent of the timing circuit in a second operation and pulling up the at least one bitline by a pull-up circuit while the sense amplifier is enabled in the second operation.

2014026, Sep 18, 2014

Mar 13, 2013

13/799532

- San Diego CA, US
Mohamed Hassan Abu-Rahma - San Diego CA, US
Fahad Ahmed - San Diego CA, US

QUALCOMM Incorporated - San Diego CA

G11C 11/419

365154

A write-assisted memory includes a pre-charge assist circuit that assists the pre-charge of the power supply voltage on a power supply lead for an accessed memory cell in a bit-line-multiplexed group of memory cells subsequent to a write-assist period by coupling charge from the power supply leads for the remaining non-accessed memory cells in the bit-line-multiplexed group of memory cells.

2014024, Sep 4, 2014

Mar 1, 2013

13/781759

- San Diego CA, US
Mohamed Hassan Abu-Rahma - San Diego CA, US
Fahad Ahmed - San Diego CA, US
Jaeyoon Kim - San Diego CA, US

QUALCOMM Incorporated - San Diego CA

G05F 3/02
G11C 7/00

365154, 327535

Various integrated circuits and methods of operating the integrated circuits are disclosed. The integrated circuit may include a circuit having one or more electrical parameters resulting from process variations during the manufacture of the integrated circuit, and a voltage source configured to supply a voltage to the circuit to power the circuit, wherein the voltage source is further configured to adjust the voltage as a function of the one or more electrical parameters.