Fred Adamic resumes & CV records
Resumes
Fred W Adamic292 Dry Creek Rd, Aptos, CA 95003
Fred Adamic Phones & Addresses
292 Dry Creek Rd, Aptos, CA 95003
608 Crescent Ave, Sunnyvale, CA 94087
Tempe, AZ
1167 Nevada Ave, San Jose, CA 95125
Social networks
Fred W Adamic
Linkedin
Work
Position:
Financial Professional
Education
Degree:
Associate degree or higher
Mentions for Fred W Adamic
Publications & IP owners
Us Patents
Silicon Sensor With Trimmable Wheatstone Bridge
US Patent:
4945762, Aug 7, 1990
Filed:
Jan 24, 1989
Appl. No.:
7/301403
Inventors:
Fred W. Adamic - Sunnyvale CA
Assignee:
SenSym, Inc. - Sunnyvale CA
International Classification:
G01L 122
G01L 906
G01L 906
US Classification:
7386267
Abstract:
A device and method for trimming diffused or implanted resistors incorporated within a silicon sensor. Current pulses are applied to cause the migration of aluminum contacts in silicon, resulting in controllable incremental reductions in resistor value. The resistors are symmetrically positioned within a Wheatstone bridge to correct offset voltage and sensitvity erros that result from manufacturing tolerances.
Inverted Dielectric Isolation Process
US Patent:
6124179, Sep 26, 2000
Filed:
Jan 30, 1998
Appl. No.:
9/016745
Inventors:
Fred W. Adamic - Santa Clara CA
International Classification:
H01L 21764
H01L 21328
H01L 21328
US Classification:
438309
Abstract:
A method of semiconductor fabrication includes the steps of forming a dielectric layer on a first surface of a semiconductor wafer having a plurality of laterally distributed semiconductor devices selectively interconnected on the first surface and bonding a support substrate to the first surface of the semiconductor wafer on the dielectric layer to form a composite structure. A portion of the semiconductor wafer from a second surface which is opposite the first surface is removed and the second surface of the semiconductor wafer is processed. Processing of the second surface optionally includes the formation of isolation trenches electrically isolating the laterally distributed semiconductor devices.
Inverted Dielectric Isolation Process
US Patent:
5841197, Nov 24, 1998
Filed:
Sep 5, 1996
Appl. No.:
8/711376
Inventors:
Fred W. Adamic - San Jose CA
International Classification:
H01L 2348
H01L 2352
H01L 2940
H01L 2900
H01L 2352
H01L 2940
H01L 2900
US Classification:
257777
Abstract:
A method of semiconductor fabrication includes the steps of forming a dielectric layer on a first surface of a semiconductor wafer having a plurality of laterally distributed semiconductor devices selectively interconnected on the first surface and bonding a support substrate to the first surface of the semiconductor wafer on the dielectric layer to form a composite structure. A portion of the semiconductor wafer from a second surface which is opposite the first surface is removed and the second surface of the semiconductor wafer is processed. Processing of the second surface optionally includes the formation of isolation trenches electrically isolating the laterally distributed semiconductor devices.
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