Gary B Nifong, Age 699 Bridlewood Rd, Durham, NC 27713

2018012, May 10, 2018

Jul 19, 2017

15/654565

- Mountain View CA, US
Jun Chen - Cary NC, US
Gary B. Nifong - Durham NC, US

G06F 17/50

Semiconductor designs are large and complex, typically consisting of numerous circuits called cells. To handle complexity, hierarchical structures are imposed on the semiconductor design to help accomplish analysis, simulation, verification, and so on. The hierarchical structures define architecture, behavior, function, structure, etc. of the semiconductor design. Virtual cells are constructed to compress cell geometries and ease the various design tasks. A cell and multiple instances of the cell are identified within the semiconductor design and the virtual hierarchical levels describing the design. Virtual hierarchical layer (VHL) data based on the cell is loaded. A virtual cell model representative of the cell is obtained. Interactions between cell data and VHL data are determined, and relevant portions of shapes are selected. Data within the virtual cell model is reduced based on the determined interactions.

2015033, Nov 26, 2015

Mar 30, 2015

14/673064

- Mountain View CA, US
James Lewis Nance - Raleigh NC, US
Gary B. Nifong - Durham NC, US

G06F 17/50

Identifying the interactions of a selected cell across a hierarchical diagram of an integrated circuit and mapping the ways in which the cell can interact with other structures in the hierarchy reduces the computational load for design rule checking (DRC) and design rules for manufacturing (DRM). To this end, a cell and multiple instances of the cell are identified within hierarchical design levels of the chip. The interactions between the cell and other cells within the hierarchy are subtracted from the cell boundary, and the results of the subtracting are merged in the cell boundary. By subtracting the results of the merging, identical interactions are identified across the multiple instances of the cell. The results of the subtracting are used to generate a virtual hierarchical layer identical (VHLi) which aids in the simulation and verification of the chip.

2015033, Nov 26, 2015

Mar 30, 2015

14/673709

- Mountain View CA, US
Jun Chen - Cary NC, US
Gary B. Nifong - Durham NC, US

G06F 17/50

Semiconductor designs are large and complex, typically consisting of numerous circuits called cells. To handle complexity, hierarchical structures are imposed on the semiconductor design to help accomplish analysis, simulation, verification, and so on. The hierarchical structures define architecture, behavior, function, structure, etc. of the semiconductor design. Virtual cells are constructed to compress cell geometries and ease the various design tasks. A cell and multiple instances of the cell are identified within the semiconductor design and the virtual hierarchical levels describing the design. Virtual hierarchical layer (VHL) data based on the cell is loaded. A virtual cell model representative of the cell is obtained. Interactions between cell data and VHL data are determined, and relevant portions of shapes are selected. Data within the virtual cell model is reduced based on the determined interactions.