George P Vakanas, Age 5814629 Jerilyn Dr, San Jose, CA 95127
George Vakanas Phones & Addresses
San Jose, CA
Mountain View, CA
Tempe, AZ
Sunnyvale, CA
Maricopa, AZ
329 W Pecan Pl, Tempe, AZ 85284 (480) 556-1537
Work
Position:
Clerical/White Collar
Education
Degree:
Associate degree or higher
Mentions for George P Vakanas
Publications & IP owners
Us Patents
Method And Apparatus For Fabrication Of Passivated Microfluidic Structures In Semiconductor Substrates
US Patent:
7446382, Nov 4, 2008
Filed:
Oct 28, 2004
Appl. No.:
10/976928
Inventors:
Paul Winer - Santa Clara CA, US
George P. Vakanas - Tempe AZ, US
George P. Vakanas - Tempe AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 27/14
H01L 29/82
H01L 29/82
US Classification:
257414, 257499
Abstract:
A method and apparatus for fabrication of passivated microfluidic structures is disclosed. The method includes providing a substrate having a microfluidic structure formed therein. The microfluidic structure is embedded by an embedding layer. The method further includes passivating the embedded microfluidic structure by locally heating the microfluidic structure surface in a reactive atmosphere, wherein the passivated microfluidic structure is suitable for transporting a fluid. The structure optionally further includes metal pads to form an electrokinetic pump.
Clipless Integrated Heat Spreader Process And Materials
US Patent:
7892883, Feb 22, 2011
Filed:
May 30, 2008
Appl. No.:
12/130822
Inventors:
George Kostiew - Chandler AZ, US
Raj Bahadur - Gilbert AZ, US
James Mellody - Phoenix AZ, US
George Vakanas - Tempe AZ, US
Leonel Arana - Phoenix AZ, US
Raj Bahadur - Gilbert AZ, US
James Mellody - Phoenix AZ, US
George Vakanas - Tempe AZ, US
Leonel Arana - Phoenix AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 21/50
H01L 21/48
H01L 21/44
H01L 21/48
H01L 21/44
US Classification:
438106, 438 15, 438 25, 438 26, 438 51, 438118, 257E21499, 257E21503
Abstract:
In one or more embodiments, a method comprising applying thermo compression to a package assembly including a lid, a die, and a package substrate to assemble the package assembly is disclosed. The method may include assembling the package assembly without coupling a biasing mechanism to the lid. Heat may be applied to a bond head coupled with a pick and place tool. Heat may be applied to a bond stage coupled to a carrier for holding the package assembly during processing. An adhesive applied to the lid or package substrate may be allowed to at least partially cure. The method may further include, in an oven, reflowing a thermal interface material (TIM) coupled to the lid and the die, curing the TIM, and/or curing the adhesive, without using clips.
Clipless Integrated Heat Spreader Process And Materials
US Patent:
8163598, Apr 24, 2012
Filed:
Jan 14, 2011
Appl. No.:
13/006541
Inventors:
George Kostiew - Chandler AZ, US
Raj Bahadur - Gilbert AZ, US
James Mellody - Phoenix AZ, US
George Vakanas - Tempe AZ, US
Leonel Arana - Phoenix AZ, US
Raj Bahadur - Gilbert AZ, US
James Mellody - Phoenix AZ, US
George Vakanas - Tempe AZ, US
Leonel Arana - Phoenix AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 21/50
H01L 21/48
H01L 21/44
H01L 21/48
H01L 21/44
US Classification:
438106, 438 15, 438118, 438119, 438122, 257E21499, 257E21506, 257E21514, 257E21519
Abstract:
In one or more embodiments, a method comprising applying thermo compression to a package assembly including a lid, a die, and a package substrate to assemble the package assembly is disclosed. The method may include assembling the package assembly without coupling a biasing mechanism to the lid. Heat may be applied to a bond head coupled with a pick and place tool. Heat may be applied to a bond stage coupled to a carrier for holding the package assembly during processing. An adhesive applied to the lid or package substrate may be allowed to at least partially cure. The method may further include, in an oven, reflowing a thermal interface material (TIM) coupled to the lid and the die, curing the TIM, and/or curing the adhesive, without using clips.
Method Of Fabricating An Identification Mark Utilizing A Liquid Film Assisted By A Laser
US Patent:
8173552, May 8, 2012
Filed:
Aug 4, 2009
Appl. No.:
12/462441
Inventors:
George P. Vakanas - Tempe AZ, US
Sergei L. Voronov - Chandler AZ, US
Luey Chon Ng - Kulim, MY
George E. Malouf - Anaheim CA, US
Sergei L. Voronov - Chandler AZ, US
Luey Chon Ng - Kulim, MY
George E. Malouf - Anaheim CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 21/31
H01L 23/544
A61N 5/00
H01L 23/544
A61N 5/00
US Classification:
438759, 438940, 257797, 2504922
Abstract:
Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a liquid on a region of a die, and then forming an identification mark through the liquid on the die.
Laser-Assisted Chemical Singulation Of A Wafer
US Patent:
8426250, Apr 23, 2013
Filed:
Oct 22, 2008
Appl. No.:
12/288627
Inventors:
George Vakanas - Tempe AZ, US
George Chen - Los Gatos CA, US
Yuval Greenzweig - Ramat Hasharon, IL
Eric Li - Chandler AZ, US
Sergei Voronov - Chandler AZ, US
George Chen - Los Gatos CA, US
Yuval Greenzweig - Ramat Hasharon, IL
Eric Li - Chandler AZ, US
Sergei Voronov - Chandler AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 21/78
US Classification:
438113, 438463, 438795, 257E21599
Abstract:
The present invention discloses an apparatus including: a laser beam directed at a wafer held by a chuck mounted on a stage inside a process chamber; a focusing mechanism for the laser beam; a steering mechanism for the laser beam; an optical scanning mechanism for the laser beam; a mechanical scanning system for the stage; an etch chemical induced by the laser beam to etch the wafer and form volatile byproducts; a gas feed line to dispense the etch chemical towards the wafer; and a gas exhaust line to remove any excess of the etch chemical and the volatile byproducts.
Microfluidic Structures In A Semiconductor Substrate And Method And Apparatus For Rapid Prototyping And Fabrication Of Same
US Patent:
2003000, Jan 2, 2003
Filed:
Jun 29, 2001
Appl. No.:
09/895127
Inventors:
Paul Winer - Santa Clara CA, US
George Vakanas - Tempe AZ, US
George Vakanas - Tempe AZ, US
International Classification:
H01L021/00
US Classification:
438/050000, 438/054000, 438/048000
Abstract:
A method and apparatus for rapid prototyping and fabrication of passivated microfluidic structures is disclosed. The method and apparatus may be used to fabricate and passivate the microfluidic channel in one system.
Wafer Singulation In High Volume Manufacturing
US Patent:
2010012, May 27, 2010
Filed:
Nov 26, 2008
Appl. No.:
12/324692
Inventors:
George Vakanas - Tempe AZ, US
George Chen - Los Gatos CA, US
Yuval Greenzweig - Hasharon, IL
Eric Li - Chandler AZ, US
Sergei Voronov - Chandler AZ, US
George Chen - Los Gatos CA, US
Yuval Greenzweig - Hasharon, IL
Eric Li - Chandler AZ, US
Sergei Voronov - Chandler AZ, US
International Classification:
H01L 21/02
B23K 26/02
B23K 26/02
US Classification:
438463, 21912167, 257E21002
Abstract:
The present invention discloses an apparatus including: a laser beam directed at a wafer held by a chuck in a process chamber; a focusing mechanism for the laser beam; a steering mechanism for the laser beam; an optical scanning mechanism for the laser beam; a mechanical scanning system for the chuck; an etch chemical induced by the laser beam to etch the wafer and form volatile byproducts; a gas feed line to dispense the etch chemical towards the wafer; and a gas exhaust line to remove any excess of the etch chemical and the volatile byproducts.
Stacked Wire-Bond Dice Attached By Pillars Or Bumps Above A Flip-Chip Die On A Semiconductor Package Substrate
US Patent:
2020009, Mar 26, 2020
Filed:
Sep 25, 2018
Appl. No.:
16/141415
Inventors:
Debendra Mallik - Chandler AZ, US
Robert L. Sankman - Phoenix AZ, US
Sanka Ganesan - Chandler AZ, US
George Vakanas - Tempe AZ, US
Omkar Karhade - Chandler AZ, US
Sri Chaitra Jyotsna Chavali - Chandler AZ, US
Zhaozhi George Li - Chandler AZ, US
Holly A. Sawyer - Aloha OR, US
Robert L. Sankman - Phoenix AZ, US
Sanka Ganesan - Chandler AZ, US
George Vakanas - Tempe AZ, US
Omkar Karhade - Chandler AZ, US
Sri Chaitra Jyotsna Chavali - Chandler AZ, US
Zhaozhi George Li - Chandler AZ, US
Holly A. Sawyer - Aloha OR, US
International Classification:
H01L 25/065
H01L 25/00
H01L 23/00
H01L 23/538
H01L 25/00
H01L 23/00
H01L 23/538
Abstract:
A wire-bond memory die is coupled to a system-on-chip processor where the processor is flip-chip mounted on a semiconductor package substrate, and the wire-bond memory die is also flip-chip configured through a redistribution layer that pins out to a series of pillars that contact the semiconductor package substrate. The wire-bond memory die is stacked on the processor and the redistribution layer overhangs the processor to contact the series of pillars.
NOTICE: You may not use PeopleBackgroundCheck or the information it provides to make decisions about employment, credit, housing or any other purpose that would require Fair Credit Reporting Act (FCRA) compliance. PeopleBackgroundCheck is not a Consumer Reporting Agency (CRA) as defined by the FCRA and does not provide consumer reports.